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參數(shù)資料
| 型號(hào)： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 46/180頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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6
PRELIMINARY
PCIset Overview
A
2.0
INTEL 450GX PCISET
3.0
HOST BUS EFFICIENCY
The Pentium Pro processor bus achieves high bus efficiency by providing support for multiple, pipelined trans-
actions. A single Pentium Pro processor may have up to four transactions outstanding at the same time, and
can be configured to support up to eight transactions active on the Pentium Pro processor bus at any one time.
The PB and MC support a choice of one or eight active transactions on the Pentium Pro processor system bus
at one time (In-Order Queue depth).
The number of transactions that can target a particular bus client is configured separately from the total number
of transactions allowed on the bus. Each PB can accept up to four transactions into its Outbound Request
Queue that target its associated PCI bus. The PB also contains a four deep Inbound Queue that holds PCI
initiated requests directed to the Pentium Pro processor bus. Each MC can accept up to four transactions that
target its associated memory space.
The Intel 450GX PCIset includes the features discussed for the Intel 450KX PCIset and provides the additional
capabilities described in this section. This PCIset consists of the 82454GX PCI Bridge (PB) and the Memory
Controller (MC). The MC for the 450GX consists of the 82453GX DRAM Controller (DC), the 82452GX Data
Path (DP), and four 82451GX Memory Interface Controllers (MIC). The 450GX permits two PBs and two MCs in
a system. In addition to parity support on the host bus described for the 450KX, the 450GX generates and
checks ECC over the host data lines. This feature can be enabled/disabled during configuration.
One aspect of the 450GX is that it can be used as a drop-in replacement for an 450KX design. Additional pins
are added in such a way that proper wiring of 450KX test pins (GTLHI, TESTLO, and TESTHI) will allow an
450GX to operate in the same system while functioning exactly as an 450KX.
GX PCI Bridge (PB)
Two 82454GX PBs can be used in a system. Dual PBs provide a modular approach to I/O performance
improvements. Compatibility versus speed are addressed with an optional compatibility operating mode to
guarantee standard bus compatible operation when needed, and allow bus concurrency when possible.
In a dual PB system, one PB is configured by strapping options at power-up to be the
Compatibility PB. This PB
provides the PC compatible path to Boot ROM and the ISA/EISA bus. The second PB is configured by the
strapping options to be the
Auxiliary PB. The Compatibility PB is the highest priority bridge to ensure a proper
response time for ISA bus masters. When two PBs are on the host bus, the Compatibility PB handles arbitration
with an internal arbiter.
GX Memory Controller (MC)
The memory configuration can be either 4-way interleaved, 2-way interleaved, or non-interleaved. Both single-
sided and double-sided SIMMs are supported. DRAM technologies up to 64Mbit at speeds of 50ns, 60ns, and
70ns can be used. Asymmetric DRAM is supported up to two bits of asymmetry (e.g., 12 row address lines and
10 column address lines). The maximum memory size is 4 Gbytes for the 4-way interleaved configuration, 2
Gbytes for the 2-way interleaved configuration, and 1 Gbyte for the non-interleaved configuration using 64 Mbit
technology. The MC provides a 64-bit data path to main memory (72-bits including ECC) for each interleave
(288 bits for a 4-way interleave design).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S82452KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Data Path Controller |
| S82453KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| S82454KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
| S8248P12NF | 功能描述:ANTENNA 824-896MHZ 8DBI N FML RoHS:是 類別:RF/IF 和 RFID >> RF 天線 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* |
| S82510 DIE | 制造商:Intel 功能描述: |
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