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參數(shù)資料
| 型號(hào)： | S82451KX |
| 廠(chǎng)商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁(yè)數(shù)： | 141/180頁(yè) |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
55
A
82454KX/GX (PB)
2.4.39 EXERRSTS—PB EXTENDED ERROR REPORTING STATUS
Address Offset:
C4–C7h
Default:
0000 0000h
Attribute:
Read/Write Clear
This register reports certain host bus error conditions. Software sets each error condition to 0 by writing 1 to it.
Bits
Description
31:21
Reserved.
20
Received Hard Failure Response. 1=Host bus hard failure response or a second AERR#
assertion was received for a PB initiated transaction. (Exception—The PB does not log a Hard Fail
Response by another host bus agent to a PB posted write. The host bus agent error registers must
be checked to determine the cause of the error.)
19
Host Bus Address Parity (AP#) Error Detected. This bit is set when an AP# parity error is
reported by the 82454.
18
Host Bus Request Parity (RP#) Error Detected. This bit is set when an RP# parity error is
reported by the 82454.
17
82454KX: Reserved.
16
Host Bus Protocol Violation Detected. This bit is set when a protocol violation, including RS
parity errors, is reported by the 82454. Both OPBs check for protocol violations in dual-bridge
82454GX systems.
15:12
Reserved.
11
82454KX: Reserved.
10
Reserved.
9
Time-out on Host Bus Detected. 1=The PB detected a time-out (no response phase within the
time-out value programmed into the PBC resister (4Ch) and In-Order Queue not empty) on the host
bus. This bit is set, regardless of whether the event is reported. This bit is not used in the auxiliary
bridge of a dual PB system.
8:4
Reserved.
3
BINIT# on Host Bus Detected. 1=BINIT# was detected on the host bus.
2
BERR# on Host Bus Detected. 1=BERR# was detected on the host bus. The PB (Compatibility
PB in an 82454GX dual PB system) generates a SERR# if enabled via bit 7 of the EXERRCMD
Register, or the PB generates BINIT if BERR# to BINIT# is enabled via bit 4 of the EXERRCMD
Register.
1
Reserved.
0
AERR# on Host Bus Detected. 1=AERR# was detected on the host bus. The PB (Compatibility
PB in an 82454GX dual PB system) generates SERR#, if enabled via bit 7 of the EXERRCMD
Register. No recovery is possible as there is a chance of data corruption.
82454GX: Host Bus Correctable Error Detected. 1=Logs a single-bit ECC error detected on the
data bus. No error is reported when a host bus correctable error is detected.
82454GX: Host Bus Uncorrectable Error Detected. 1=Logs a multiple-bit ECC error detected on
the data bus. Note that this bit is set independent of whether error reporting is enabled via bit 11 of
the EXERRCMD Register. If BERR# is enabled in the CSCONFV and EXERRCMD Registers, this
error is reported by generating a BERR#.
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