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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 161/180頁 |
| 文件大小： | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
73
A
82454KX/GX (PB)
3.7.5
USING THE 82379AB SIO.A PCI-TO-ISA BRIDGE WITH THE 450KX/GX
There is an anomaly with systems that use the 82379AB (SIO.A) during targeted PCI Resets. In addition,
450GX/KX systems can boot improperly at power-up and react improperly to the assertion of the Pentium Pro
bus signal BINIT# signal (due to the assertion of PCIRST# via BINIT#).
The SIO.A drives SMI#, ALT_A20, INT, NMI, IGNNE#, ALT_RST#, and STPCLK# low while PCIRST# is
asserted low, and does not drive them high until after PCI reset is released. An anomaly can exist with these
seven signals remaining low during and immediately after PCIRST# is negated. The three instances in which
this can cause an anomaly are: during a targeted PCI Reset, and in a 450GX/KX-Pentium Pro processor
system, both during power-up and when BINIT# is asserted on the Pentium Pro processor bus.
Power-Up
During power up of an 450GX/KX-Pentium Pro system, the OPB negates PCIRST# and RESET# (to the
Pentium Pro) simultaneously. The delay in negating these seven signals after PCIRST# is driven inactive can
cause these signals to be sampled active low by the Pentium Pro when RESET# (to the Pentium Pro) is
released.
SMI#: When SMI# is sampled low at power-up, the Pentium Pro attempts to jump to the SMI handler
instead of to the boot vector. An external solution is necessary to avoid this erroneous power-up
condition. Essentially, SMI# must be blocked from being sampled low by the CPU when RESET# is
driven inactive. If SMI# is not being used, the SMI# input to the CPU can be pulled high. For systems
using SMI#, the solution shown below on the SMI# signal ensures that SMI# is high when RESET#
transitions inactive.
This solution is not needed in systems using Pentium Pro B0 stepping (or later). These steppings of the
Pentium Pro will not sample these seven inputs for at least 300ns after RESET# is negated.
ALT_RST#: The CPU will reset again (generates INIT# to the Pentium Pro). This signal must be
blocked. This solution is not needed in systems using Pentium Pro B0 stepping (or later). These
steppings of the Pentium Pro will not sample these seven inputs for at least 300ns after RESET# is
negated.
INT: Not an issue since this signal remains low following PCIRST#.
NMI: Not an issue since this signal remains low following PCIRST#.
IGNNE#: Has no affect on the processor when sampled low during power-up.
ALT_A20: Has no affect on the processor when sampled low during power-up.
STPCLK#: Has no affect on the processor when sampled low during power-up.
BINIT# Assertion
When BINIT# is asserted by an agent on the Pentium Pro processor bus, the 82454KX/GX asserts PCIRST# to
reset the PCI Bus. The SIO.A drives SMI#, ALT_A20, INT, NMI, IGNNE#, ALT_RST#, and STPCLK# low while
PCIRST# is asserted low, and does not drive these signals high until after PCI reset is released. Several of
these signals must be blocked with external logic if the system architecture cannot handle them going low as a
result of BINIT#. Architectural Considerations consist primarily of how the system’s Pentium Pro processors
have been configured to handle the assertion of BINIT# and how any external error handling logic might
influence the need for blocking logic. All steppings of the Pentium Pro processor need these solutions (where
appropriate) if BINIT# is to be handled.
ALT_RST#: The low assertion of this signal causes the Pentium Pro processor to be reset each time
BINIT# is asserted on the Pentium Pro processor bus (this signal is combined with INIT# from the PB to
generate the INIT# signal to the Pentium Pro processor). This signal MUST be blocked with external
logic if the system architecture cannot handle this.
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