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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 12/180頁 |
| 文件大小： | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
101
A
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
2.0
MC REGISTER DESCRIPTION
The MC contains two sets of registers (I/O space registers and configuration registers) that are accessed via
the host CPU I/O address space. Accessing MC configuration registers uses the same procedure as is defined
for accessing PCI device configuration registers (e.g., for the PB). The required PCI Header register set is
provided permitting the MC to respond to initialization software in the same manner as an actual PCI device
(i.e., the MC register set is PCI compliant). In some cases, (e.g., PCICMD register), the register may only be
appropriate for a device attached to the PCI bus. In these cases the register is shown as a read only register
with the bits hardwired appropriately and writes have no effect.
The I/O space registers (CONFADD and CONFDATA Registers) provide indirect access to the MC configu-
ration registers. The MC’s internal registers can be accessed as Byte, Word (16-bit), or Dword (32-bit)
quantities, with the exception of CONFADD which can only be accessed as a Dword. 0-length I/O reads are not
supported by the MC. The following nomenclature is used for access attributes.
RO
Read Only. If a register is read only, writes to this register have no effect.
R/W
Read/Write. A register with this attribute can be read and written.
R/WC
Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1
clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
Some of the MC registers contain reserved bits. Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any
particular value. On writes, unless otherwise specified in the individual register descriptions, software must
ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must
first be read, merged with new values for other bit positions and written back. In some cases, software must
program reserved bit positions to a particular value. This value is defined in the individual bit descriptions.
In addition to reserved bits within a register, the MC contains address locations in the MC’s configuration space
that are marked “Reserved”. The MC responds to accesses to these address locations by completing the host
transaction. Software should not write to reserved MC configuration locations in the device-specific region
(above address offset 3Fh).
2.1
Initialization and Configuration
After a power-on reset, the type of memory assumed is non-interleaved. The default DRAM timing values for
the non-interleaved memory are set to reasonable values for 66 MHz and slow memory. It is expected that the
BIOS will change these default memory timing values as necessary before memory is accessed. For the
450KX, the memory base address is hardwired to zero. For the 450GX, each MC memory base address is
determined at reset according to its controller number (strapping option on the OMCNUM signal). After the
power-on initialization, system BIOS determines memory size and configuration and programs the configu-
ration registers accordingly. After a power-on reset, the MC is set for a 4 Mbyte main memory size. The 512
Kbyte DOS RAM region and accesses from 1 Mbyte to 4 Mbytes are enabled (MC accepts accesses). Until
initialized, the MC does not respond to any other memory locations.
The MC and PB residing on the host bus contain a configuration space that is compliant with the configuration
space in the PCI bus specification. While the MC is not a true PCI device, it uses the same configuration
register access mechanism. The VID Register (00–01h) and the DID Register (02–03h) both return legitimate
values.
The MC has two registers located in I/O Space—The Configuration Address (CONFADD) Register and the
Configuration Data (CONFDATA) Register. The compatibility PB is the only response agent for host accesses
to CONFADD and the MC snoops writes to this register. CONFADD is first written to select the MC. A
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