- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98071 > S82451KX (INTEL CORP) SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 PDF資料下載
參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 38/180頁 |
| 文件大小： | 1094K |
| 代理商： | S82451KX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁
124
PRELIMINARY
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
A
High BIOS (HBIOS) Register. The 64 Kbyte region from F0000–FFFFFh is treated as a single block
and is normally Read/Write disabled in the MC(s) and Read/Write enabled in the PB. After power-on
reset, this region is R/W enabled in the PB (Compatibility PB only in the 450GX and R/W disabled in the
Auxiliary PB). Thus, the PB can respond to fetches during system initialization. The Read/Write
attributes for this region may be used in conjunction with the Read/Write attributes in the PB to “shadow”
BIOS into RAM.
I/O APIC Range (APICR) Register. This register provides an I/O APIC configuration space. There is no
I/O APIC in the PB or the MC.
DRAM Row Limit (DRL) Registers. These registers define the upper and lower addresses for each
DRAM row and represent the boundary addresses in 4 Mbyte granularity.
If a memory space access is in one of the above ranges, and that range is enabled for memory access, the MC
claims the transaction and becomes the response agent.
The MC performs memory recovery on gap ranges greater than or equal to 1 Mbyte that are created by the
Low Memory Gap, Memory Gap, and the High Memory Gap areas. This memory is relocated to the top of the
MC’s memory. The MC performs a subtraction of the size of the hole in the memory map to generate an
effective memory address.
Note that the PB (Compatibility PB in an 450GX dual PB system) is responsible for claiming any unclaimed
transactions on the host system bus. Therefore, any memory space access that is above the top of system
main memory is claimed by the PB.
The MC has two registers located in the processor’s I/O space (0CF8h and 0CFCh) that are used to configure
the MC. See the Register Descripiton section for details.
3.2
Host Bus Interface
The Pentium Pro processor bus provides an efficient, reliable interconnect between multiple Pentium Pro
processors and the PB and MC. The bus provides 36 bits of address, 64 bits of data, protection signals needed
to support data integrity, and the control signals to maintain a coherent shared memory in the presence of
multiple caches.
The Pentium Pro processor bus achieves high bus efficiency by providing support for multiple, pipelined trans-
actions and deferred replies. A single Pentium Pro processor may have up to four transactions outstanding at
the same time, and can be configured to support up to eight transactions active on the Pentium Pro processor
bus at any one time. The MC supports up to four transactions that target its associated memory space. The MC
contains read and write buffers for memory accesses.
For the 450GX, the base address for the MC that is not MC #0 must include the size of any memory gaps
programmed in the previous (or lower base address) MC.
There can be up to two MCs in a system permitting up to 8 Gbytes of system main memory. The portion of the
processor’s memory space controlled by an MC is determined by the Base Address Register and memory size.
In a PC architecture, the only restrictions on MC placement are that there be memory starting at address 0 and
that there be enough memory to operate a system. The MCs in a system need not have contiguous address
spaces. The High Memory Gap in one MC could be used to span the gap between the top of its memory map
and the base address of the other MC.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S83296SA | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100 |
| SB83296SA | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100 |
| S83C196MH | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| S83C51FB-BB44 | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP44 |
| S83C51FC-5B44 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S82452KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Data Path Controller |
| S82453KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| S82454KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
| S8248P12NF | 功能描述:ANTENNA 824-896MHZ 8DBI N FML RoHS:是 類別:RF/IF 和 RFID >> RF 天線 系列:* 標準包裝:1 系列:* |
| S82510 DIE | 制造商:Intel 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。