- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98071 > S82451KX (INTEL CORP) SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 PDF資料下載
參數(shù)資料
| 型號(hào)： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁(yè)數(shù)： | 140/180頁(yè) |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)當(dāng)前第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)
54
PRELIMINARY
82454KX/GX (PB)
A
Bits
Description
31:14
Reserved.
13
Report Errors using Hard Fail/SERR# Enable. 1=Enable (Hard Fail mechanism). 0=Disable (PB
uses SERR#). These errors are reported when the PB is servicing a host bus request and detects
an error. Note that the PB does not report PERR# through Hard Fail.
12
Report PCI Master Abort Errors. 1=Enable. 0=Disable. When enabled, the PB normally returns all
1’s to CPU read transactions that receive a master abort time-out. Note that bit 13 in the PCISTS
Register is always set for master abort time-outs. The error reporting mechanism (Hard Fail or
SERR#) is determined by bit 13 of this register.
11
82454KX: Reserved.
10
82454KX: Reserved.
9
Report Host Bus Time-out Errors Enable. 1=Enable. 0=Disable. When enabled, the error
reporting mechanism (Hard Fail or SERR#) is determined by bit 13 of this register. Note that the PB
normally returns all 1’s to CPU read transactions that receive a time-out. Bit 9 in the EXERRSTS
Register is set, regardless of whether the error is reported.
8
Host Bus Time-out Enable. 1=The PB responds to unclaimed host bus transactions when the Bus
watchdog timer expires. The time-out value can be programmed to either 1.5 ms or 30 ms.
0=Disable watchdog timer.
7
AERR# to NMI Enable. 1=Enable. 0=Disable. When enabled (and bit 8=1 in the Captured System
Configuration Values Register and SERR# is enabled in the PCICMD Register), the PB (Compati-
bility PB in an 82454GX dual PB system) asserts the SERR# signal when detecting AERR# signal
asserted. Note that, depending on the system architecture, the SERR# signal can result in the
generation of an NMI. The NMI signal is not part of the PB and is typically provided by a PCI-to-ISA
or PCI-to-EISA bridge.
6
BERR# to NMI Enable. 1=Enable. 0=Disable. When enabled (and bit 9=1 in the CSCONFV
Register, offset B4–B5h), the PB (Compatibility PB in an 82454GX dual PB system) asserts the
SERR# signal (which can result in an NMI) when BERR# is asserted. Note that the NMI signal is not
part of the PB. NMI is typically provided by a PCI-to-ISA or PCI-to-EISA bridge.
5
Reserved.
4
BERR# to BINIT# Enable. 1=Enable. 0=Disable. When enabled, the PB asserts BINIT# when
BERR# is asserted.
3
Assert BINIT# on Detection of Host Bus Protocol Violations Enable. 1=Enable. 0=Disable.
2
Assert BERR# on Bus Errors Enable. 1=Enable. 0=Disable.
1
Reserved. Planned use is AERR# to BERR# Enable. 1=Enable. 0=Disable.
0
Assert AERR# on Request Phase Signal Parity Errors Enable. 1=Enable. 0=Disable.
82454GX: Report Uncorrectable Host Data Bus ECC Errors. 1=Report by BERR# signal (bit 2
must be set to 1). 0=Disable
82454GX: Single-bit ECC Error Correcting of Host Data Bus Enable. 1=Enable. 0=Disable.
For the 82454GX in a dual PB system, this bit only has affect in the Compatibility PB and has no
affect in the Auxiliary PB
Caution: Programming this bit must be consistent with the value in the corresponding bit of the
CSCONFV Register captured from the host bus. Otherwise, incorrect system operations will result.
Caution: Programming this bit must be consistent with the value in the corresponding bit of the
CSCONFV Register captured from the host bus. Otherwise, incorrect system operations will result.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S83296SA | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100 |
| SB83296SA | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100 |
| S83C196MH | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| S83C51FB-BB44 | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP44 |
| S83C51FC-5B44 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S82452KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Data Path Controller |
| S82453KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| S82454KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
| S8248P12NF | 功能描述:ANTENNA 824-896MHZ 8DBI N FML RoHS:是 類別:RF/IF 和 RFID >> RF 天線 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* |
| S82510 DIE | 制造商:Intel 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。