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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 145/180頁 |
| 文件大小： | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
59
A
82454KX/GX (PB)
3.1.2
I/O ADDRESS MAP
The Pentium Pro processor I/O address space is 64 Kbytes. For the 82454KX, the PB maps all host bus I/O
accesses to the PCI bus, except for the CONFADD, CONFDATA, and TRC Register locations.
The PB registers that control the I/O space accesses are:
CONFADD, CONFDATA, and TRC Registers. These three PB registers are located in the processors
I/O address space. See the Register Description section for details.
PCI Decode Mode (PDM) Register. The PB optionally supports ISA expansion aliasing. When ISA
expansion aliasing is enabled (via the PDM Register), the ranges designated as I/O Expansion are
internally aliased to the 100–3FFh range before the I/O Space Range registers are checked.
CPU Transactions to I/O Space. For the 82454KX, the PB claims all host bus I/O accesses and forwards the
accesses to the PCI bus, except for the CONFADD, CONFDATA, and TRC Register locations. Accesses to
CONFADD (OCF8) must be Dword aligned. I/O Transactions targeting 0CF8h are treated as normal I/O trans-
actions when they are not Dword aligned. Accesses to CONFDATA (0CFCh) are treated as normal I/O transac-
tions when the Configuration Space Enable bit of the CONFADD Register is not set.
ISA Expansion Board Aliasing. In PCs the I/O address range 100–3FFh is reserved for ISA Expansion
boards. Many ISA Expansion boards only decode address bits [9:0] which results in aliases of the decode
range of these boards. The PB provides a method to route the alias of an address in the 100–3FFh range
through the appropriate PB when I/O space has been split between dual PBs. See PCI Decode Mode (PDM)
Register (offset 48h).
PCI Transactions to I/O Space. For the 82454KX, I/O space accesses are never forwarded to the host bus.
For the 82454GX, the Compatibility PB maps all host bus I/O accesses to the PCI bus, except for I/O address
ranges programmed into the IOSR[2:1] Registers (and the CONFADD, CONFDATA, and TRC Register
locations). In a dual PB system, the Auxiliary PB ignores all host bus I/O accesses (except for the CONFADD
and CONFDATA Register locations), unless forwarding is programmed into the IOSR[2:1] Registers.
I/O Space Range Registers (IOSR[2:1]). Two I/O Space Range Registers (IOSR1 and IOSR2) permit
the PB to forward transactions targeting that range to the PCI bus.
If an I/O space address is in either of the I/O ranges, and that range is enabled, the PB claims the transaction
and forward it to the PCI bus. For the 82454GX in a dual PB system, the Compatibility PB is the default I/O
response agent responsible for claiming all I/O transactions on the host system bus. Therefore, any I/O
address range that is mapped to an Auxiliary PB must be disabled by an I/O range register in the Compatibility
PB.
When using the I/O Space Range Registers, the CONFADD, CONFDATA, and TRC Registers (0CF8h, 0CF9h,
and 0CFCh) are treated differently than other I/O space addresses. I/O Transactions targeting 0CF8h are
treated as normal I/O transactions by the IOSR[2:1] Registers when they are not Dword aligned transactions.
Accesses to 0CFCh are treated as normal I/O transactions by the IOSR[2:1] Registers when the Configuration
Space Enable bit of the CONFADD Register is not set. Byte address OCF9h is recognized only by the Compat-
ibility PB, and is never affected by the IOSR[2:1] Registers.
For the Auxiliary PB in a dual PB system, all PCI I/O space accesses are forwarded to the host bus unless they
are specifically directed to PCI by one of the I/O Range registers. For the Compatibility PB, I/O space accesses
are never forwarded to the host bus, unless specifically directed to the host bus by one of the I/O Range
registers. The PB never forwards PCI I/O accesses greater than 64 Kbytes to the host bus.
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