
PRELIMINARY
25
A
82454KX/GX (PB)
1.2
Signal State During Reset
Table 6 shows the state of all PB output and bi-directional signals during a hard reset (RESET# asserted).
NOTES:
1. During a power-on reset, A[12:5]# are inputs providing configuration information. For the 82454KX/GX, during a pro-
grammed hard reset (via the Compatibility PB’s TRC register), the Compatibility PB drives these signals and the all other
host bus devices sample these signals.
2. For the 82454GX during a power-on reset, IOGNT# and IOREQ# are inputs used to set the PB configuration mode.
3. For the 82454GX after a power-on reset, RESET# is an output from all PBs until the PBs have read in their PBID from the
IOGNT# and IOREQ# signals. After the PBs receive their PBID, RESET# is an output from the Compatibility PB and an
input to the Auxiliary PBs.
4. During a power-on reset, INIT# is driven inactive. The PB can be programmed (via the TRC Register) to drive this signal low
during a programmed hard reset to invoke CPU Built-In Self Test (BIST).
5. These signals not used in the Auxiliary bridge in 82450GX systems.
6. Tri-state during PWRGD inactive.
Table 6. Signal State During Reset
Signal
State
Signal
State
A[35:3]#
Not Driven1
AD[31:0]
Not Driven
ADS#
Not Driven
AERR#
Not Driven
AP[1:0]
Not Driven
BERR#
Not Driven
BINIT#
Not Driven
BNR#
Not Driven
BPRI#
Not Driven
C/BE[3:0]#
Not Driven
CRESET#
Low5
D[63:0]#
Not Driven
DBSY#
Not Driven
DEFER#
Not Driven
DEP[7:0]#
Not Driven
DEVSEL#
Not Driven
DRDY#
Not Driven
FLUSH#
High5
FRAME#
Not Driven
HIT#
Not Driven
HITM#
Not Driven
IOREQ#
Input2
INIT#
High5
IRDY#
Not Driven
LOCK#
Not Driven
MEMACK#
Not Driven
PAR
Not Driven
PCIRST#
Low
PCLK
Driven6
PERR#
Not Driven
PLOCK
Not Driven
PREQ#
Not Driven
PTRDY#
Not Driven
RESET#
Low3
REQ[4:0]#
Not Driven
RP#
Not Driven
RS[2:0]#
Not Driven
RSP#
Not Driven
SERR#
Not Driven
SMIACT#
High5
STOP#
Not Driven
TDO
Tri-state during TRST#
TRDY#
Not Driven