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參數(shù)資料
| 型號(hào)： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁(yè)數(shù)： | 41/180頁(yè) |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
127
A
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
3.3.1
DRAM CONFIGURATIONS
The memory supported by the MC is arranged as 4 rows with 1 or 2 interleaves (8 rows with 1, 2, or 4 inter-
leaves for the 450GX). This can be implemented with discrete memory devices, single-sided SIMMs, or double-
sided SIMMs. Systems in which adjacent rows of memory have a common CAS# connection are a special
case, and are selected via the CMD Register (offset 4C–4Fh). The primary example of this is a system
constructed with double-sided SIMMs having a common CAS# connection between the two sides.
For all the memory configuration types, the MC provides 4 logical RAS# signals (8 for the 450GX); one per row.
Two copies of the RAS# signals (RASAx# and RASBx#) are provided for fanout. The MC provides 4 logical
CAS# signals (8 for the 450GX). Two copies (CASAx# and CASBx#) are provided for fanout.
In the case of a common CAS# connection between adjacent rows, there are only 2 logical CAS# signals (one
per pair of rows) for the 450KX and 4 logical CAS# signals for the 450GX. In addition, the loading per CAS#
signal is doubled. To accommodate this, the MC combines the CAS# signals for two rows (e.g. CASA[1:0#] and
CASB[1:0]#) are driven with the same value and are used to drive the first two memory rows.
The descriptions of the supported configurations that follow assume that the DRAM in the system is imple-
mented with double-sided SIMMs that do not have a common CAS# connection and that do not have buffers
on the SIMMs. Figure 2 shows the connections required for each double-sided SIMM (DSSIMM). Note that
these are SIMM connections and do not map one-to-one to MC signals. Also shown is the symbol used to
represent the 72-bit wide memory formed from two DSSIMMs.
Figure 2. Signal Connections to a Double-Sided SIMM
3.3.1.1 Memory Interface Component (MIC)
To interface with the data signals from the devices in the memory array, the MC utilizes a set of four Memory
Interface Components (MICs), each 18 bits wide. These components multiplex data read from the interleaved
memory, register data being written to memory, and provide the buffering required to drive the memory devices.
All configurations utilize four of these devices. The interconnection of the MICs and the memory devices is
shown in Figure 3.
D[35:0]
A[12:0]
WE#
RAS[x:x-1]#
CAS[x:x-1]#
Two DSSIMMs
(word-wide
e.g., 72 bits)
相關(guān)PDF資料 |
PDF描述 |
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| S83296SA | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100 |
| SB83296SA | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100 |
| S83C196MH | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| S83C51FB-BB44 | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP44 |
| S83C51FC-5B44 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S82452KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Data Path Controller |
| S82453KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| S82454KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
| S8248P12NF | 功能描述:ANTENNA 824-896MHZ 8DBI N FML RoHS:是 類別:RF/IF 和 RFID >> RF 天線 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* |
| S82510 DIE | 制造商:Intel 功能描述: |
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