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參數(shù)資料
| 型號(hào)： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁(yè)數(shù)： | 143/180頁(yè) |
| 文件大小： | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
57
A
82454KX/GX (PB)
3.0
PB FUNCTIONAL DESCRIPTION
This section describes the PB functions and hardware interfaces including the I/O and Memory Map, Host bus,
PCI bus, and Dual-bridge Architectures. Data Integrity and Error Handling are covered. Clock, Reset, and PB
configuration are also covered.
3.1
Memory and I/O Map
The 82454KX/GX PB provides the interface between the host bus and the PCI bus. Memory transactions can
be sent from the PCI bus to the host bus and from the host bus to the PCI bus. Gaps and positive decode
ranges can be programmed via the configuration registers. For the 82454KX, I/O transactions can be sent from
the host bus to the PCI bus. However, I/O transactions can not be sent from the PCI bus to the host bus.
If an access is enabled to be forwarded from the host bus to the PCI bus, the corresponding access on the PCI
bus is ignored (not forwarded to the host bus). Conversely, if an access is enabled to be forwarded from the
PCI bus to the host bus, the corresponding access on the host bus is ignored (not forwarded to the PCI bus).
The PB and MC perform a positive address decode of each host transaction and one default device handles
the unclaimed transactions. In a standard PC system, unclaimed transactions are sent to the ISA bus. Thus,
the PB (Compatibility PB in an 82454GX dual PB system) is the default responder on the host bus.
3.1.1
MEMORY ADDRESS MAP
The Pentium Pro processor memory address space is 64 Gigabytes (36-bit addressing). The PB does not
support transactions of address size larger than 36-bits whether directed to the PB or not. The PB registers that
control the memory space access are:
Programmable Attribute Map (PAM[6:0]) Registers. These registers provide Read Only, Write Only,
and Read/Write Disable for fixed memory regions in the PC compatibility area.
Video Buffer Area Enable (VBA) Register. This register enables the A0000–BFFFF fixed region.
Top System Memory (TSM) Register. This register permits the PB (Compatibility PB in an 82454GX
dual PB system) to claim memory transactions above the top of main memory (top of memory to 64
Gbytes) and forward these transactions to the PCI Bus.
Memory Gap Range Registers (MGR and MGUA Registers). The Memory Gap Range can start on
any 1 Mbyte boundary from 1 Mbyte to 64 Gbytes and can be 1, 2, 4, 8,16, or 32 Mbytes.
High Memory Gap Range Registers (HMGSA and HMGEA Registers). The High Memory Gap can
start on any 1 Mbyte boundary from 1 Mbyte to 64 Gbytes.
High BIOS (HBIOS) Register. The 64 KByte region from F0000–FFFFFh is treated as a single block
and is normally read/write disabled in the MC(s) and Read/Write enabled in the PB.
For the 82454GX, both memory and I/O transactions can be sent from the PCI bus to the host bus and from the
host bus to the PCI bus. Memory and I/O gaps and positive decode ranges can be programmed via the config-
uration registers.
After power-on reset, this region is read/write enabled in the Compatibility PB and read/write disabled
in the Auxiliary PB. Thus, the Compatibility PB responds to fetches during system initialization.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| S82452KX | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Data Path Controller |
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| S82454KX | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:PCI Bus Interface/Controller |
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