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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 152/180頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
65
A
82454KX/GX (PB)
3.5
Dual PB Architectures (82454GX Only)
In a dual bridge system, one PB is configured as the default bridge (Compatibility PB) after power-on RESET.
The Compatibility PB provides a path to the ISA bus devices needed in a PC-compatible system such as the
boot ROM. The Compatibility PB is the highest priority bridge in a dual bridge system to ensure a fast enough
response time for ISA bus masters. See the Clocks, Reset, and Configuration section for details on config-
uring a PB as the Compatibility PB.
Multiple I/O APICs
In a dual PB system, the auxiliary PCI bus interrupt requests are routed to the auxiliary bus I/O APIC. When
booting the system with one processor, the IRQ control logic is enabled, feeding the interrupt request to the
standard interrupt controller in the ESC. When the system is in multiprocessor mode, the routing logic is
disabled after ensuring PB buffer coherency, and interrupt requests are forwarded to the processors via the
APIC bus. The Intel 82379AB (SIO.A) may be utilized as a stand-alone I/O APIC device. However, the
additional logic for interrupt/memory consistency and the interrupt steering logic is not provided in the SIO.A
and must be implemented externally.
Dual Bridge Arbitration for the Host Address Bus
The PB requests the host address bus with BPRI#. However, only one bridge is allowed to drive BPRI# at a
time. With two PBs, an internal arbiter is used to establish bus ownership. This arbitration is transparent to the
CPU and other symmetric bus agents.
In a two PB system, the compatibility PB acts as the arbitration unit between it and the other PB, as shown in
Figure 6. When a PB is programmed to be the arbitration unit, its IOGNT# is the input for the IOREQ# from the
other bridge and IOREQ# is the output to IOGNT# of the other bridge.
Figure 7 shows the minimum arbitration timing in a two bridge system. IOGNT# may assert later than shown
and IOREQ# may negate later than the two clocks after IOGNT# negates.
The arbiter bridge can assert BPRI# as long as it has not asserted its IOREQ# (Grant to the other bridge) and
BPRI# is not currently driven. In turn, the other bridge, after receiving it’s IOGNT#, samples BPRI# released
before assuming ownership of BPRI#. This allows the BPRI# arbitration to be performed in parallel with
another bridge transfer. This timing is shown in Figure 8.
Bridge-to-bridge misaligned (split) locks are not recommended and could cause deadlock in systems.
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