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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 57/180頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
7
A
PCIset Overview
Both the PB and MC provide four 32-byte buffers for outbound data and four 32-byte buffers for inbound data.
For the PB, the outbound data refers to CPU-to-PCI writes or PCI reads from the CPU bus and inbound data
refers to PCI-to-CPU writes or CPU reads from PCI. For the MC outbound data refers to CPU writes to main
memory and inbound data refers to CPU reads of main memory.
The maximum data transfer that is supported by the Pentium Pro processor bus is four 64-bit wide transfers.
This transfer satisfies the 32-byte cache line size of the Pentium Pro processor interface. The Pentium Pro
processor supports operations that are not completed in the order in which they were requested. This ‘deferred
response’ capability allows the Pentium Pro processor bus to be freed to execute other requests while waiting
for the response from a request to a device with relatively long latency. Note that the 450 PCIset does not defer
requests to itself, nor does it (the PB) allow its transactions to be deferred.
4.0
SYSTEM MEMORY MAP
A Pentium Pro processor system can have up to 64 Gbytes of addressable memory. The lower 1 Mbyte of this
memory address space is divided into regions that can be individually controlled with programmable attributes
such as disable, read/write, write only, or read only.
At the highest level, the address space is divided into four conceptual regions as shown in Figure 2. These are
the 0–1 Mbyte Compatibility Area, the 1 Mbyte to 16 Mbyte Extended Memory region used by ISA, the 16
Mbyte to 4 Gbyte Extended Memory region used by EISA, and the 4 Gbyte to 64 Gbyte Extended Memory
introduced by 36 bit addressing. Each of the regions are divided into subregions, as described in the following
sections.
Figure 2. Pentium Pro Processor Memory Address Space.
For the 450GX, up to two MCs can be placed in the address space spanned by these regions. In a PC archi-
tecture, the only restrictions on memory placement are that there be memory starting at address 0 and that
there be enough memory to operate a system. The MCs in a system need not have contiguous address
spaces. Each MC also supports two memory ranges for the memory connected to the MC, by providing a high
memory gap range register that defines the space between the two ranges of memory. This range effectively
defines the top address for the lower memory range and the base address for the upper memory range.
Compatibility
Area
Extended
Memory
(ISA)
Extended
Memory
(EISA)
1MB
15MB
4GB - 16MB
100_0000
0
F_FFFF
FF_FFFF
10_0000
Extended
Memory
(above 4GB)
64GB - 4GB
F_FFFF_FFFF
1_0000_0000
FFFF_FFFF
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