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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 156/180頁 |
| 文件大小： | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
69
A
82454KX/GX (PB)
3.6.2
DISTRIBUTING PERIPHERALS WITHIN THE I/O SUBSYSTEM
While this is not necessary for system operation, systems implementing dual 82454 PBs have additional
latitude to isolate high speed I/O devices from competing system traffic initiated by the CPU.
All graphics and the vast majority of I/O space communication (such as keyboard controller, system timer, and
interrupt support) will be directed to the
primary PCI bus behind the Compatibility 82454 PB. (This is the bus
with a subsequent connection via another bridge to an ISA or EISA bus.) This processor traffic will compete
with bus mastering peripheral devices attempting to move data to and from system memory. It is desirable then
to place latency sensitive devices behind the
Auxiliary 82454 PB, to isolate them from competing CPU traffic.
In a full system configuration, in which all PCI slots are occupied, it is preferable to segregate peripherals intel-
ligently. Limit the primary PCI bus to graphics accelerators and SCSI RAID controllers, leaving Auxiliary
82454 PB PCI slots free for latency-sensitive devices such as network adapters. In systems connecting a large
number of network adapters, divide them evenly between the two busses to minimize the amount of latency-
sensitive competition at any one point in the system.
3.6.3
PCI-TO-PCI BRIDGES
Since PCI-to-PCI bridge (P2P) components are a popular mechanism for increasing the connectivity of a PCI
subsystem, the issues associated with using them should be understood. Note that these components are not
only used on motherboards, but are sometimes used on PCI adapters as well.
The hierarchical bus added into the system in this manner must compete with all other devices on the primary
bus for bandwidth. Further, the devices sharing the additional PCI bus connected via the P2P must compete
with each other for serial service across the P2P bridge. This means that peripherals placed behind a P2P
device will perceive higher latency to memory and will be limited to shorter burst transfers; a condition which
may cause errors in latency-sensitive peripherals.
Finally, if a P2P device in use is not fully compliant with the PCI 2.1 specification, the system is exposed to
unresolvable conflicts between multiple bus masters issuing transactions attempting to cross between the
hierarchical PCI busses. To eliminate the possibility of a resulting livelock failure, the system must operate with
CPU-PCI write posting disabled. This will degrade the performance of outbound traffic such as graphics, but will
not adversely affect the performance of bus mastering I/O devices.
3.6.4
BIOS PERFORMANCE TUNING
Specific system configurations each have an optimum set of performance feature settings, but the following
recommendations establishes a good baseline to begin system tuning.
The system designer should tune the read prefetch enable bits in the 82454 to avoid wasted host bus
bandwidth due to short reads that do not make use of prefetched data. Most PCI peripherals which implement
the advanced PCI command set also use these commands as recommended in the PCI specification. Specifi-
cally, PCI masters should use the PCI memory read command for transfers less than a cache line in length, the
PCI memory read line command for transfers of one or two cache lines, and the PCI memory read multiple
command for transfers of two or more cache lines. Given no specific data on the peripherals to be used in the
system, the BIOS should default to a configuration which assumes that PCI peripherals will behave as
described above. That is, enable the line read alias bits for all PCI read command types, but only enable the
read prefetch bit for the PCI memory read multiple command. This configuration may be modified, perhaps in a
setup utility, if that provides better performance for a given set of devices.
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