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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 155/180頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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68
PRELIMINARY
82454KX/GX (PB)
A
.
3.6
Peripheral Operation and Performance
The 82454 PB is designed for optimum processor performance to get the most out of a Pentium Pro
processor’s capabilities. In systems with multiple PCI devices, one must take into account the architecture of
the 82454 PB in order to maximize overall system performance.
3.6.1
MATCHING PERIPHERALS TO THE 450KX/GX
The 82454 PB is optimized for use with high performance PCI peripherals. Support for multiple CPUs and
multiple 82454 PBs comes at the cost of greater latency to system memory, which must be offset by more
efficient use of the PCI bus to achieve high bandwidth I/O throughput.
For best system performance, only devices meeting the following criteria should be used in conjunction with the
82454 PB:
1.
High throughput peripherals should be PCI bus masters that control their own DMA. Peripherals
which act as bus masters transfer data to and from memory with minimal intervention from the CPU. The
available bandwidth for such devices is considerably greater than that available to
programmed-I/O
devices, which require the CPU to transfer data on their behalf. Bus mastering devices also allow the CPU
to pursue other work in parallel with I/O transfers from PCI, resulting in higher overall system efficiency.
Finally, outbound traffic from the CPU interferes with inbound bus mastering transactions, as they both
compete for ownership of the 82454 PB. The latter effect implies that one non-mastering device can
adversely impact the performance of several other mastering devices.
2.
Peripherals should support the advanced PCI command subset. The advanced PCI commands are
Memory Read Line (command encoding E), Memory Read Multiple (command encoding C), and Memory
Write and Invalidate (command encoding F). Devices utilizing these commands differentiate between long
data transfers and short overhead transfers, and use appropriate PCI commands for each. Further, such
devices tend to implement sufficient on-board data FIFO space to support full-speed PCI burst transfers
greater than a cache line in length.
3.
Latency-sensitive peripherals should provide adequate data buffering. Peripherals such as network
interface cards have a latency requirement once transmission has begun. If they cannot buffer sufficient
data on board prior to initiating a transfer, they are subject to transmission under-runs when competing I/O
subsystem activity causes the bandwidth across the wire to exceed the bandwidth into system memory. A
similar scenario occurs in the opposite direction if the bandwidth into system memory falls below the band-
width across the wire. For example, a PCI card supporting
fast ethernet at 100 Mbit/sec, should provide at
least 128 bytes of data buffering for transfers in each direction.
Table 10. Bridge Device Number Encoding
IOGNT#
IOREQ#
PBID
(BDNUM Register)
Description
High
Low
01
Compatibility PB
Low
High
10
Auxiliary PB in a two PB system
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