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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 101/180頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
19
A
82454KX/GX (PB)
1.0
PB SIGNAL DESCRIPTIONS
This section contains a detailed description of each signal. The signals are arranged in functional groups
according to their interface.
Note that the ‘#’ symbol at the end of a signal name indicates that the active, or asserted state occurs when the
signal is at a low voltage level. When ‘#’ is not present at the end of a signal name, the signal is asserted when
at the high voltage level.
The terms assertion and negation are used extensively. This is done to avoid confusion when working with a
mixture of ‘a(chǎn)ctive-low’ and ‘a(chǎn)ctive-high’ signals. The term assert, or assertion indicates that a signal is active,
independent of whether that level is represented by a high or low voltage. The term negate, or negation
indicates that a signal is inactive.
The following notations are used to describe the signal type.
I
Input is a standard input-only signal.
O
Totem Pole Output is a standard active driver.
I/O
Input/Output is bi-directional, tri-state signal.
GTL+
GTL+ Processor bus signal defined for 1.5V operation.
CMOS
Rail-to-Rail
CMOS Tolerant to 5V levels.
PCI
CMOS signal specifically meeting PCI Specification 2.0.
Analog
Reference Voltage.
1.1
PB Signals
Table 1. Host Bus Interface Signals
Signal
Type
Description
A[35:3]#
I/O,
GTL+
ADDRESS BUS. A[35:3]# contains the transaction address on the clock cycle with
ADS# asserted. Byte enables, deferred ID, and additional transaction information
are encoded on these lines during the cycle following ADS#. Note that the PB never
asserts Defer Enable when it is a bus master.
ADS#
I/O,
GTL+
ADDRESS STROBE. ADS# is asserted during the first cycle of the Request Phase
to indicate valid address and command signals.
AERR#
I/O,
GTL+
ADDRESS ERROR. AERR# is asserted by any agent that detects an address parity
error, If enabled in the EXERRCMD Register.
AP[1:0]#
I/O,
GTL+
ADDRESS PARITY. AP1# covers A[35:24]# and AP0# covers A[23:3]#. AP[1:0]# is
valid on both cycles of the request.
BERR#
I/O,
GTL+
BUS ERROR. BERR# is asserted by any agent that observes an unrecoverable bus
protocol violation, if enabled in the EXERRCMD Register.
BINIT#
I/O,
GTL+
BUS INITIALIZATION. BINIT# is asserted to re-initialize the bus. The PB
terminates any ongoing PCI transaction at this time and resets its inbound and
outbound queues. No configuration registers or error logging registers are affected.
BNR#
I/O,
GTL+
BLOCK NEXT REQUEST. BNR# is asserted by an agent to prevent the request
bus owner from issuing further requests.
BPRI#
I/O,
GTL+
PRIORITY AGENT BUS REQUEST. BPRI# is issued by the high priority bus agent
to acquire the request bus. The high priority agent is always the next bus owner.
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