
vi
PRELIMINARY
A
2.3.10 SMME—SMRAM Enable Register .....................................................................................110
2.3.11 VBRE—Video Buffer Region Enable Register ...................................................................110
2.3.12 PAM[0:6]—Programmable Attribute Map Registers ...........................................................110
2.3.13 DRL—DRAM Row Limit (0 to 7) .........................................................................................111
2.3.14 SBCERRADD—Single Bit Correctable Error Address Register .........................................112
2.3.15 MG—Memory Gap Register ..............................................................................................113
2.3.16 MGUA—Memory Gap Upper Address Register .................................................................114
2.3.17 LMG—Low Memory Gap Register .....................................................................................114
2.3.18 HMGSA—High Memory Gap Start Address Register ........................................................115
2.3.19 HMGEA—High Memory Gap End Address Register .........................................................115
2.3.20 APICR—I/O APIC Range Register ....................................................................................115
2.3.21 UERRADD—Uncorrectable Error Address Register ..........................................................116
2.3.22 MEMTIM—Memory Timing Register ..................................................................................116
2.3.23 SMMR—SMRAM Range Register .....................................................................................119
2.3.24 HBIOSR—High BIOS Gap Range Register .......................................................................119
2.3.25 MERRCMD—Memory Error Reporting Command ............................................................120
2.3.26 MERRSTS—Memory Error Status Register ......................................................................120
2.3.27 SERRCMD—System Error Reporting Command Register ................................................121
2.3.28 SERRSTS—System Error Status Register ........................................................................122
2.4 Memory Configuration Determination Algorithm .............................................................................122
3.0 MC Functional Description ..................................................................................................................123
3.1 Memory and I/O Map ......................................................................................................................123
3.2 Host Bus Interface ..........................................................................................................................124
3.3 DRAM Interface ..............................................................................................................................125
3.3.1 DRAM Configurations ..........................................................................................................127
3.3.1.1 Memory Interface Component (MIC) ......................................................................127
3.3.1.2 4-Way DRAM Configuration (450GX Only) .............................................................128
3.3.1.3 2-Way DRAM configuration ....................................................................................129
3.3.1.4 Non-Interleaved DRAM configuration .....................................................................130
3.4 Clocks and Reset ............................................................................................................................131
3.4.1 Clocks ..................................................................................................................................131
3.4.2 Reset ....................................................................................................................................131
4.0 MC Pinout and Package Information ..................................................................................................132
4.1 82453KX/82453GX (DC) Pin Assignment ......................................................................................132
4.2 82452GX/82452KX (DP) Pin Assignment ......................................................................................135
4.3 82451GX/82451KX (MIC) Pin Assignment .....................................................................................142
4.4 82453GX/82453KX (DC) Package Dimensions ..............................................................................145
4.5 82452GX/82452KX (DP) Package Dimensions ..............................................................................146
4.6 82451GX/82451KX (MIC) Package Dimensions ............................................................................148