
152
PRELIMINARY
PCIset Electrical Specifications
A
1.2.1
THE POWER GOOD SIGNAL— PWRGD
PWRGD is a 3.3V input to the PCI Bridge and memory controller components. It is expected that this signal is
a clean indication that the clocks and the 3.3V, VCCPCI supplies are within their specifications. ‘Clean’ implies
that PWRGD will remain low, (capable of sinking leakage current) without glitches, from the time that the power
supplies are turned on until they become valid. The signal will then transition monotonically to a high (3.3V)
state with the transition not taking longer than 100ns. PWRGD needs to be negated for at least 10 BCLKs
before this transition from low to high can take place. Figure 1 illustrates the relationship of PWRGD to BCLK
and the system reset signals.
The PWRGD inputs to the Intel 450KX/GX PCIsets and to the Pentium Pro Processor(s) should be driven with
an “AND” of ‘Power-Good’ signals from the 5V, 3.3V and VCCP supplies. The output of this logic should be a
3.3V level and should have a pull-down resistor at the output to cover the period when this logic is not receiving
power.
1. Italicized signals are inputs on one device and I/O on another device: A[35:3]#, ADS#, AP[1:0]#, REQ[4:0]#, RP#, and
RESET# are inputs to the DC, and I/O on the PB. MIRST# is an output from the DC and an input to the DP and MICs.
2. SBCERR# is an open-drain signal.
3. PCI signals are both 3.3V and 5V tolerant. The drive and receive strength for the PCI signals is set by the VCCPCI input
(PCIBus voltage). For additional details, see the PCI Local Bus Specification, Rev 2.0.
CMOS Output, 12mA, 5V
Tolerant
CRESET#, MEMACK#, PREQ#
CMOS Output, 12mA, 3.3V
CASA[7:0]#, CASB[7:0]#, MA0[12:0], MA1[12:0], MICMWC[1:0]#,
RASA[7:0]#, RASB[7:0]#, RESET#, SBCERR#, SYSDEN#,
WE[1:0]#
(2)
CMOS Output, 18mA, 3.3V
MDRDY[1:0]#, MICCMD[6:0]#, MIRST#
CMOS I/O, 6mA, 5V Tolerant
PCLK
CMOS I/O, 6mA, 3.3V
MEMCMD[7:0]#
CMOS I/O, 12mA, 5V Tolerant
I0D[17:0], I1D[17:0], I2D[17:0], I3D[17:0]
CMOS I/O, 12mA, 3.3V
IOREQ#, MDE[71:0]
PCI Signals, 24mA
AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, IRDY#, PAR, PERR#,
PLOCK#, PTRDY#, SERR#, STOP#
(3)
Power
GND, GTLVREF, VCC3, VCCPCI
Table 1. Signal Groups (Continued)
Pin Group
Signals
Notes