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參數(shù)資料
| 型號(hào)： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁(yè)數(shù)： | 162/180頁(yè) |
| 文件大小： | 1094K |
| 代理商： | S82451KX |
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74
PRELIMINARY
82454KX/GX (PB)
A
INT: Not a problem since this signal remains low following PCIRST#. Note that any pending interrupts
on this pin will be lost when the SIO receives the PCI reset.
NMI: Not a problem since this signal remains low following PCIRST#. Note that any pending interrupts
on this pin will be lost when the SIO receives the PCI reset.
IGNNE#: Unless software or the system architecture can ensure that no floating point errors are
generated during the PCI reset, this signal must be blocked.
ALT_A20: Designers must be aware that this signal will be driven (and remain) low during and following
PCIRST#. Additionally, RSTDRV is asserted during PCIRST#. This sill cause the RSTAR# output of the
keyboard controller to also be set low. These factors must be considered in any design implementing
BINIT# functions.
STPCLK#: If the STPCLK# function is enabled in the design, then this signal must incorporate blocking
logic.
SMI#: If SMI# is enabled in the design, then this signal must incorporate blocking logic.
Targeted PCI Resets
Systems that support targeted PCI Resets (Resetting the PCI bus via Software control without resetting the
microprocessor) may have a problem with some of the seven signals being asserted low during the targeted
PCI reset. Since the microprocessor can not know when a PCIRST is occurring, this fix must be incorporated in
order to reset the PCI bus via the register. This affects all designs using the SIO.A.
ALT_RST#: The low assertion of this signal will cause the microprocessor to be reset each time the PCI
bus is reset (this signal is normally combined with a CPU soft reset pin from another component to
generate the INIT# signal to the microprocessor). This signal MUST be blocked with external logic.
INT: Not an issue since this signal remains low following PCIRST#. Note that any pending interrupts on
this pin will be lost when the SIO receives the PCI reset.
NMI: Not an issue since this signal remains low following PCIRST#. Note that any pending interrupts on
this pin will be lost when the SIO receives the PCI reset.
IGNNE#: Unless software or the system architecture can ensure that no floating point errors are
generated during the PCI bus reset, this signal must be blocked.
ALT_A20: Designers must be aware that this signal will be driven (and remain) low during and following
PCIRST#. Additionally, RSTDRV is asserted during PCIRST#. This sill cause the RSTAR# output of the
keyboard controller to also be set low. These factors must be considered in any design implementing
targeted PCI resets.
STPCLK#: If the STPCLK# function is enabled in the design and it is not desirable to have the CPU
“shutdown” throughout the PCI reset, then this signal must incorporate blocking logic.
SMI#: If SMI# is enabled in the design, then this signal must incorporate blocking logic.
The RESET MASK blocking circuit shown in Figure 12 will block signal A from being seen by the CPU during
the PCI Reset. The second flip flop is necessary to avoid a glitch on the Z output to the CPU which can happen
if signal A is asserted simultaneously with PCIRST#.
The blocking circuitry for all of the signals should be incorporated into a PLD. This will ease loading on PCICLK
and PCIRST#.
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相關(guān)代理商/技術(shù)參數(shù) |
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