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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 35/180頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
5
A
PCIset Overview
1.0
INTEL 450KX PCISET
The 450KX desktop PCIset consists of the 82454KX PCI Bridge (PB) and the Memory Controller (MC). The MC
consists of the 82453KX DRAM Controller (DC), the 82452KX Data Path (DP), and four 82451KX Memory
Interface Components (MIC). The system configuration using the Intel 450KX PCIset supports one PB, one MC
and up to two Pentium Pro processors (Figure 1). An ISA subsystem is also located below the PB. For Pentium
Pro processor bus error detection, the 450KX generates and checks parity over the address and
request/response signal lines. This feature can be enabled/disabled during system configuration.
KX PCI Bridge (PB)
The PB is a single-chip host-to-PCI Bridge. A rich set of CPU-to-PCI and PCI-to-CPU bus transaction transla-
tions optimize bus bandwidth and improve system performance. All ISA and EISA regions are supported. Three
programmable memory gaps can be created—a PCI Frame Buffer Region with specialized frame buffer
attributes and two general-purpose memory gaps (called the Memory Gap Region and the High Memory Gap
Region).
The PB takes advantage of the Pentium Pro processor ratio clocking scheme to assure modularity now and
upgradability in the future. The PB has a synchronous interface to the Pentium Pro processor bus and supports
a derived clock for the synchronous PCI interface. The PB derives either a 30 or 33 MHz PCI clock output from
the Pentium Pro processor bus clock. The PB PCI signals are 5 volt tolerant and can be used with either 5 volt
or 3.3 volt PCI devices.
KX Memory Controller (MC)
The combined MC (DC, DP, and four MICs) act as one physical load on the Pentium Pro processor bus. The
DC provides control for the DRAM memory subsystem, the DP provides the data path, and the four MICs are
used to interface the MC datapath with the DRAM memory subsystem.
The memory configuration can be either 2-way interleaved or non-interleaved. Both single-sided and double-
sided SIMMs are supported. DRAM technologies up to 64 Mbits at speeds of 50ns, 60ns, and 70ns can be
used. Asymmetric DRAM is supported up to two bits of asymmetry (e.g., 12 row address lines and 10 column
address lines). The maximum memory size is 1 Gbyte for the 2-way interleaved configuration and 512 Mbytes
for the non-interleaved configuration using 16 Mbit technology. In addition to these memory configurations, the
MC provides data integrity features including ECC in the memory array. These features, as well as a set of
error reporting mechanisms, can be selected via configuration of the MC. Each interleave provides a 64-bit
data path to main memory (72-bits including ECC).
The MC is PC compatible. All ISA and EISA regions are decoded and shadowed based on programmable
configurations. Regions above 1 Mbyte with size 1 Mbyte or larger that are not mapped to memory may be
reclaimed by setting the appropriate configuration in the MC. Three programmable memory gaps can be
created and are called the
Low Memory Gap Region, the Memory Gap Region and the High Memory Gap
Region.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S82452KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Data Path Controller |
| S82453KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| S82454KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
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| S82510 DIE | 制造商:Intel 功能描述: |
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