- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98071 > S82451KX (INTEL CORP) SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 PDF資料下載
參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 149/180頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁當(dāng)前第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁
62
PRELIMINARY
82454KX/GX (PB)
A
3.4
Data Integrity and Error Handling
Several data integrity features are included in the PB. These include ECC on the host data bus (450GX only),
parity on the host address, parity on the CPU Request/Response signals, and parity on the PCI bus. Error
logging (setting a status bit) and reporting (generating an error signal) are controlled by the PCICMD Register
(04–05h), PCISTS Register (06–07h), ERRCMD Register (70h), ERRSTS Register (71h), EXERRCMD
Register (C0–C3h), and EXERRSTS Register (C4–C7h).
3.4.1
HOST BUS ERRORS
The PB detects errors on the host bus by checking the ECC provided with data (450GX only) and the parity
provided with control signals. In turn, the PB will generate ECC with data (450GX only) and parity with control
signals so that bus errors can be detected by receiving clients.
Request Parity (RP#) is the parity signal for ADS# and REQ[4:0]# and is computed as even parity. AP[1:0]# are
the parity signals for A[35:3]# and are computed as even parity (AP1# is for A[35:24]# and AP0# is for A[23:3]#.
RSP# is the parity signal for RS[2:0]# and is computed as even parity. In addition, certain host bus protocol
violations are detected by the PB.
The PB (Compatibility PB in a 82454GX dual PB system) is responsible for responding to any unclaimed trans-
actions on the host bus. The PB uses a watchdog timer to monitor host response phases. The timer is started
at the end of a response phase if the In-Order Queue is not empty. If the timer expires before the next host
response phase, a host bus time-out has occurred. The time-out window for such an event is programmable to
1.5 or 30 milliseconds via the PBC Register (4Ch). This allows for several host to PCI transactions, which may
be blocking the progress of the In-Order Queue, to undergo multiple retries. When a host bus time-out occurs,
the PB (Compatibility PB in an 450GX dual PB system) claims the transaction by returning all 1’s to a read
transaction or “pretending” to accept data for a write transaction. This event is logged in the EXERRSTS
Register and can generate a hard fail or SERR#, if enabled in the EXERRCMD Register.
AERR#. If AERR# observation is enabled, then AERR# to NMI should be enabled in the EXERRCMD register
(C0-C3h). This allows software to accept an NMI to log or recover from the event.
BINIT#. A BINIT# on the Host bus creates a PCIRST# and resets the 450KX/GX PCIset host bus state
machines. This allows for logging or recovery from catastrophic bus errors.
3.4.2
PCI BUS ERRORS
The PB always detects address parity errors when it is not the PCI master, even if it is not the selected target.
The PB detects data parity errors if it is either the master or the target of a transaction, and optionally reports
them to the system. Address parity errors are reported using the SERR# signal. Data parity errors are reported
using the PERR# signal.
On the 450GX, ECC error checking is used for the data bus. The ECC check bits are provided by the
DEP[7:0]# signals.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S83296SA | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100 |
| SB83296SA | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100 |
| S83C196MH | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| S83C51FB-BB44 | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP44 |
| S83C51FC-5B44 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S82452KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Data Path Controller |
| S82453KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| S82454KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
| S8248P12NF | 功能描述:ANTENNA 824-896MHZ 8DBI N FML RoHS:是 類別:RF/IF 和 RFID >> RF 天線 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* |
| S82510 DIE | 制造商:Intel 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。