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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 147/180頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
61
A
82454KX/GX (PB)
3.3
PCI Bus Interface
The PB has a standard master/slave PCI bus interface. All legal PCI (PCI specification 2.0) bus transactions
are supported. PCI cycle termination and error logging/reporting are discussed in the Data Integrity and Error
Handling section. The PCI arbitration unit is not implemented in the PB.
PCI Locks. Systems which support PCI initiate locks (either inbound locks or peer-to-peer) must configure the
arbiter for full bus locks rather than resource locks. The PB will not recognize resource locks made by peer-to-
peer accesses. When a PCI master asserts LOCK# while targeting the PB, the locked PCI transactions are
converted to locked host bus transactions. The host bus lock continues as long as the PCI master asserts
LOCK# for exclusive access to the PB. The host bus lock is assisted by the bridge continuing to assert BPRI#
as long as the PCI bus is asserting resource lock to the bridge. Additional locked CPU transactions are issued
if the PCI master continues to burst.
In systems in which target abort reporting is disabled, the write portion of a lock will be committed even when
the read portion is aborted.
NOTE:
Locks that cross cache line boundaries initiated on the PCI bus will not generate a SPLCK# signal on the
host bus. This should be understood by all host bus agents. Neither the PB nor the MC require SPLCK#
assertion.
Host Bus Locks. Any transactions that target the bridge during a host bus lock are converted into a similar PCI
lock transaction. The lock on the PCI bus is held until the host bus lock is released. Locks over the Frame
Buffer region can be disabled through a mode bit in the PCI Frame Buffer Range Register.
NOTE:
Locks that split across PCI host bus device boundaries (originate to one device and complete to another)
are only supported for shadowed memory, and then only behind the compatibility PB. Shadowed memory
is memory mapped for read only or write only in the MC and the opposite way in the PB. An update may
be required for older non-PCI 2.0 compliant device drivers to comply with this. Since the revision 2.0 of the
PCI specification does not allow locks to cross device boundaries, this will not be an issue with new device
drivers.
Indivisible Operations. CPU initiated read operations that cross a Dword boundary (e.g., Read 8 Bytes, Read
16 Bytes, etc.) are indivisible operations on the host bus. However, since the PCI protocol allows a target
device to disconnect at any point in a transfer sequence, these operations must be locked indivisible on the PCI
bus. The PB optionally locks all CPU initiated reads that cross a Dword boundary. This mode is enabled by
setting the Lock Atomic Reads in the PB Configuration Register. CPU initiated Write operations (e.g., Write 8
Bytes, Write 16 Bytes, etc.) are indivisible operations on the host bus. However, these accesses can not be
made indivisible on the PCI bus because the PCI Specification states that the first transaction of a locked
operation must be a read. Therefore, software must not rely upon the atomicity of CPU initiated write transac-
tions greater then 32 bits once they are translated to the PCI bus.
Software Generated Special Cycles. This optional feature is not supported by the 450KX/GX PCIset.
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