
112
PRELIMINARY
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
A
2.3.14 SBCERRADD—SINGLE BIT CORRECTABLE ERROR ADDRESS REGISTER
Address Offset:
74–77h
Default:
0000h
Attribute:
Read Only
This register provides the effective address of the memory access that caused a single bit correctable error on
the memory side. The value in this register is only valid if the SBC correctable error bit is set in the MERRSTS
Register (C2–C3h).
Bits
Description
15:7
Reserved.
6:0
DRAM Row Upper Address Limit (in units of 4 Mbytes). This 7-bit field determines the upper
address limit of a particular row (i.e., DRL minus previous DRL = row size). Note that the allowed
minimum and maximum values for row size depend on the memory configuration (non-interleaved
row size = 4 Mbytes minimum and 128 Mbytes maximum; 2-way interleaved row size = 8 Mbytes
minimum and 256 Mbytes maximum).
Example:
Row 0 has 16 Mbytes, row 1 is unpopulated, and row 2 has 32 Mbytes. The DRL Registers would
be programmed as follows:
DRL0 = 04h
DRL1 = 04h
DRL[2:7]= 0Ch (each register)
Bits
Description
15:11
Reserved.
10:0
DRAM Row Upper Address Limit (in units of 4 Mbytes). This 11-bit field determines the upper
address limit of a particular row (i.e., DRL minus previous DRL = row size). Note that the allowed
minimum and maximum values for row size depend on the memory configuration (non-interleaved
row size = 4 Mbytes minimum and 128 Mbytes maximum; 2-way interleaved row size = 8 Mbytes
minimum and 256 Mbytes maximum; 4-way interleaved = 16 Mbytes minimum and 512 Mbytes
maximum).
Example:
In a 4-way interleaved configuration with all rows containing 512 Mbytes, the DRL Registers would
be programmed as follows:
DRL0 = 80h
DRL4 = 280h
DRL1 = 100h
DRL5 = 300h
DRL2 = 180h
DRL6 = 380h
DRL3 = 200h
DRL7 = 400h