
72
PRELIMINARY
82454KX/GX (PB)
A
Programmed Hard Reset
The PB (Compatibility PB in an 82454GX dual PB system) can be programmed to deliver a hard reset (assert
RESET#) to the host bus through the TRC Register. Note that the internal register values are reset.
Programmed Soft Reset (INIT#)
The PB (Compatibility PB in an 82454GX dual PB system) can be programmed to deliver a soft reset (INIT#) to
the processors through the TRC Register. Note that the internal register values are preserved.
Programmed PCI Bus Reset
The PB (both PBs in an 82454GX dual PB system) can be programmed to reset their PCI buses (assert
PCIRST#) without resetting the host bus (via the PCI Reset Register). Note that internal register values are
preserved.
Programmed CPU BIST
The PB (Compatibility PB in an 82454GX dual PB system) can be programmed to put the processor into BIST
mode via the TRC Register. CPU BIST is triggered by performing a hard reset and having the INIT# signal
asserted on the edge that RESET# is released. Note all 450KX/GX PCIset devices are reset during the hard
reset portion of this operation.
3.7.3
SYSTEM INITIALIZATION
All host bus devices must sample the following configuration options at reset:
Address/request/response parity checking: Enabled or Disabled
AERR detection enable
BERR detection enable
BINIT detection enable
FRC mode: Enabled or Disabled
Power-on reset vector: 1M or 4G
In-Order Queue depth: 1 or 8
APIC cluster ID: 0, 1, 2, or 3
Symmetric agent arbitration ID: 0, 1, 2, 3
The MC provides the Symmetric Arbitration ID parameter. The PB provides some of the other parameters. See
Configuration Values Driven on Reset Register.
3.7.4
DUAL PB CONFIGURATION (82454GX ONLY)
During a power-on reset (PWRGD asserted), IOREQ# and IOGNT# provide a unique identification number for
each PB (PBID). See Dual PB Architectures Section for details.