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參數(shù)資料
| 型號(hào)： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁(yè)數(shù)： | 39/180頁(yè) |
| 文件大小： | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
125
A
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
NOTES:
1.
The MC does not generate deferred responses.
2.
The MC does not provide the ability to abort a transaction during the response phase.
3.
On the host bus, a Hard Failure Response is generated for failures in accessing a resource. Such a failure
could be a time-out after requesting a device that is not available. Note that data failures do not fall into a
hard failure class. The MC does not generate Hard Failure responses.
4.
All transactions in the MC are processed in “address” order with respect to when they are received on the
host bus. There is reordering of read-around-writes, but only when the address of the read is different
from the address of the write. If there is an address conflict, the transactions are processed in the order
they are received. (Note, responses to transactions still occur in the order in which they were received,
only the processing of the requests is reordered.)
5.
The MC does not respond to an SMI Acknowledge Transaction or Stop Clock Acknowledge Transaction,
even though they are encoded as memory type operations on the host bus.
AERR#. An AERR# on the host bus stops traffic in the memory controller. Reporting is done by the 82454 (PB).
BINIT#. A BINIT# on the Host bus resets the 450KX/GX host bus state machines. This allows for logging or
recovery from catastrophic bus errors. Note that during the last clock of a BINIT# pulse, ADS# may not be
asserted as this will start the host bus state machine prematurely.
3.3
DRAM Interface
In the following discussion the term
row refers to the set of memory devices that are simultaneously selected by
a RAS# signal. A row may be composed of two or more single-sided SIMMs, or one side (the same side) from
two or more double-sided SIMMs. An
interleave is 72-bits wide (64 data bits plus 8 bits of ECC) and requires
two 36 bit SIMMs. The term
page refers to the data within a row that is selected by a row address and is held
active in the device waiting for a column address to be asserted.
The MC interfaces the main memory DRAM to the host bus. For the 450KX, two basic DRAM configurations
are supported—2-way interleaved (or 2:1 interleaved), and non-interleaved (or 1:1 interleaved). In the 2-way
and non-interleaved configurations, a row is made up of 4 SIMM sides and 2 SIMM sides respectively. There
can be up to 1 Gbyte of DRAM for a 2-way interleaved configuration and 512 Mbytes of DRAM for a non-inter-
leaved configuration as shown in Table 22. The MC is fully configurable through the MC’s configuration
registers.
Configurations cannot be mixed. The MC does not support portions of the memory being 2-way interleaved and
other portions being non-interleaved. The system does, however, support a 2-way interleaved design in which
one interleave is populated (operates as a non-interleaved configuration). There is no restriction on which
interleave is populated (0 or 1) to form a non-interleaved configuration, as long as all rows are populated in the
same way.
For the 450GX, three basic DRAM configurations are supported—4-way interleaved (4:1 interleaved), 2-way
interleaved, and non-interleaved. In the 4-way interleaved configuration, a row is made up of 8 36-bit SIMM
sides. In the 2-way interleaved and non-interleaved configurations, a row is made up of 4 SIMM sides and 2
SIMM sides respectively. There can be up to 4 Gbytes of DRAM for a 4-way interleaved configuration,
2Gbytes for a 2-way interleaved configuration, and 1Gbyte for a non-interleaved configuration.
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