
PRELIMINARY
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A
3.6 Peripheral Operation and Performance ............................................................................................68
3.6.1 Matching Peripherals to the 450KX/GX .................................................................................68
3.6.2 Distributing Peripherals Within the I/O Subsystem .................................................................69
3.6.3 PCI-to-PCI Bridges ................................................................................................................69
3.6.4 BIOS Performance Tuning ......................................................................................................69
3.7 Clock, Reset, and Configuration .......................................................................................................70
3.7.1 System clocking .....................................................................................................................70
3.7.1.1 Host Bus Clock .........................................................................................................70
3.7.1.2 PCI Clock ..................................................................................................................71
3.7.2 System Reset .........................................................................................................................71
3.7.3 System Initialization ...............................................................................................................72
3.7.4 Dual PB Configuration (82454GX only) .................................................................................72
3.7.5 Using the 82379AB SIO.A PCI-to-ISA Bridge with the 450KX/GX .........................................73
3.8 Host to PCI Bus Command Translation ............................................................................................76
3.9 PCI to Host Bus Command Translation ............................................................................................77
4.0 PB Pinout and Package Information .....................................................................................................79
4.1 Pin Assignment .................................................................................................................................79
4.2 Package Information .........................................................................................................................87
Chapter 3
Memory Controller (MC)
1.0 MC Signal Description ...........................................................................................................................93
1.1 DC Signals ........................................................................................................................................93
1.2 DP Signals ........................................................................................................................................96
1.3 MIC Signals ......................................................................................................................................98
1.4 Signal State During Reset ..............................................................................................................100
2.0 MC Register Description ......................................................................................................................101
2.1 Initialization and Configuration ........................................................................................................101
2.2 I/O Space Registers ........................................................................................................................102
2.2.1 CONFADD—Configuration Address Register ......................................................................103
2.2.2 CONFDATA—Configuration Data Register ..........................................................................103
2.3 MC Configuration Registers ............................................................................................................104
2.3.1 VID—Vendor Identification Register .....................................................................................105
2.3.2 DID—Device Identification Register .....................................................................................105
2.3.3 PCICMD—PCI Command Register .....................................................................................106
2.3.4 PCISTS—PCI Status Register .............................................................................................106
2.3.5 RID—Revision Identification Register ..................................................................................106
2.3.6 CLASSC—Class Code Register ..........................................................................................107
2.3.7 BASEADD—MC Base Address Register (450GX only) .......................................................107
2.3.8 CDNUM—Controller Device Number Register ....................................................................108
2.3.9 CMD—Command Register ..................................................................................................108