
PRELIMINARY
XRT86SH328
87
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
This RESET-upon-READ register, along with Receive Transport - B2 Byte Error Count Register - Bytes 3, 2 and 0,
function as a 32 bit counter, which is incremented anytime the Receive STS-1/STS-3 TOH Processor block detects a
B2 byte or BIP-24 error within the incoming STS-1/STS-3 data-stream.
N
OTES
:
1.
If the Receive STS-1/STS-3 TOH Processror block is configured to count B2 byte errors on a per-bit
basis, then it will increment this 32 bit counter by the number of bits, within the B2 byte (of each incoming
STS-1/STS-3 frame) that are in error.
2.
If the Receive STS-1/STS-3 TOH Processor block is configured to count B2 byte errors on a per-frame
basis, then it will increment this 32 bit counter each time that it receives an STS-1/STS-3 frame that contains
an erred B2 byte or erred BIP-24.
BIT [7:0] - B2 Byte Error Count - LSB
This RESET-upon-READ register, along with Receive Transport - B2 Byte Error Count Register - Bytes 3 through 1,
function as a 32 bit counter, which is incremented anytime the Receive STS-1/STS-3 TOH Processor block detects a
B2 byte or BIP-24 error within the incoming STS-1/STS-3 data-stream.
N
OTES
:
1.
If the Receive STS-1/STS-3 TOH Processor block is configured to count B2 byte errors on a per-bit
basis, then it will increment this 32 bit counter by the number of bits, within the B2 byte (of each incoming
STS-1/STS-3 frame) that are in error.
2.
If the Receive STS-1/STS-3 TOH Processor block is configured to count B2 byte errors on a per-frame
basis, then it will increment this 32 bit counter each time that it receives an STS-1/STS-3 frame that contains
an erred B2 byte or erred BIP-24.
BIT [7:0] - REI-L Event Count - MSB
This RESET-upon-READ register, along with Receive STS-1/STS-3 Transport - REI-L Event Count Register - Bytes 2
through 0, function as a 32 bit counter, which is incremented anytime the Receive STS-1/STS-3 TOH Processor block
detects a Line - Remote Error Indicator event within the incoming STS-1 or STS-3 data-stream.
N
OTES
:
1.
If the Receive STS-1/STS-3 TOH Processor block is configured to count REI-L events on a per-bit basis,
then it will increment this 32 bit counter by the nibble-value within the REI-L field of the M0 byte within each
incoming STS-1/STS-3 frame.
2.
If the Receive STS-1/STS-3 TOH Processor block is configured to count REI-L events on a per-frame
basis, then it will increment this 32 bit counter each time that it receives an STS-1 or STS-3 frame that
contains a non-zero REI-L value.
T
ABLE
89: R
ECEIVE
STS-1/STS-3 T
RANSPORT
- B2 B
YTE
E
RROR
C
OUNT
R
EGISTER
- B
YTE
0 (A
DDRESS
L
OCATION
= 0
X
0217)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B2_Byte_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
90: R
ECEIVE
STS-1/STS-3 T
RANSPORT
- REI-L E
VENT
C
OUNT
R
EGISTER
- B
YTE
3 (A
DDRESS
L
OCATION
=
0
X
0218)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI-L_Event_Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0