
PRELIMINARY
XRT86SH328
167
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
This READ-ONLY bit-field indicates whether or not the VT-Mapper Pattern Receiver is currently declaring Pattern Sync
with the incoming Test Signal.
`
0 - VT-Mapper Pattern Receiver is NOT currently declaring Pattern Sync with the incoming Test Signal.
`
1 - VT-Mapper Pattern Receiver is currently declaring Pattern Sync with the incoming Test Signal.
BIT[6:0] - Test Pattern Error Count[14:8]:
These seven (7) RESET-upon-READ bit-fields, along with the Test Pattern Error Count[7:0] bit-fields function as a 15-
bit Pattern Bit Error Count Register. If the VT-Mapper Pattern Receiver is currently declaring Pattern Sync with the
designated Test Signal, then it will increment this register (by the value of 1) each time that it detects Pattern Bit Error.
These seven (7) bit-fields function as the seven most-significant bits of this 15-bit counter.
BIT[7:0] - Test Pattern Error Count[7:0]:
These eight (8) RESET-upon-READ bit-fields, along with the Test Pattern Error Count[14:8] bit-fields function as a 15-
bit Pattern Bit Error Count Register. If the VT-Mapper Pattern Receiver is currently declaring Pattern Sync with the
designated Test Signal, then it will increment this register (by the value of 1) each time that it detects Pattern Bit Error.
These eight (8) bit-fields function as the eight least-significant bits of this 15-bit counter.
Bits 7 - 6 - Unused:
BIT[5:4] - Transmit Tributary Size Select for VT# 6[1:0]:
These two READ/WRITE bit-fields are used to specify the VT-size (or the bit-rate to be supported by) that the Transmit
VT-Mapper block (associated with Virtual Tributary Group # 6) will support.
N
OTE
:
This configuration setting only applies to the Transmit VT-Mapper block. This configuration setting does not
configure the Receive VT-De-Mapper block to expect any particular VT-type within VT Group # 6. The user
T
ABLE
222: G
LOBAL
C
ONTROL
- VT-M
APPER
- T
EST
P
ATTERN
D
ETECTOR
E
RROR
C
OUNT
R
EGISTER
- L
OWER
B
YTE
(A
DDRESS
= 0
X
0C17)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Test Pattern Error Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
223: G
LOBAL
C
ONTROL
- VT-M
APPER
- T
RANSMIT
T
RIBUTARY
S
IZE
S
ELECT
R
EGISTER
(A
DDRESS
=
0
X
0C1A)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
TxTributary Size Select -
VT#6[1:0]
TxTributary Size Select -
VT#5[1:0]
TxTributary Size Select -
VT#4[1:0]
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
1
1
1
1
Size of VT #6
T
X
T
RIBUTARY
S
IZE
S
ELECT
- VT#6[1:0]
R
ESULTING
S
IZE
OF
VT # 6
00
VT-6
01
VT-3
10
VT-2/TU-12
11
VT-1.5/TU-11