
PRELIMINARY
XRT86SH328
51
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
BIT 7 - T1/E1 De-Sync Disable
This READ/WRITE bit-field is used to either enable or disable the T1/E1 De-Sync Circuitry within the XRT86SH328.
`
0 - Enables the T1/E1 De-Sync Circuitry.
`
1 - Disables the T1/E1 De-Sync Circuitry.
BIT 6 - STS-1/STS-3 and DS3 Share Serial Interface
This READ/WRITE bit-field is used to configure the DS3 and STS-1/STS-3 circuitry to either share the same Serial
Interface or not. To operate the XRT86SH328 in the Transmux mode, then the user must configure the DS3 and STS-
1/STS-3 circuitry to NOT share the same Serial Interface.
`
0 - Configures the STS-1/STS-3 and DS3 circuitry to NOT share the same Serial Interface.
`
1 - Configures the STS-1/STS-3 and DS3 circuitry to Share the same Serial Interface.
BIT
5 -
Additional T1/E1 Framer Enabled
This READ/WRITE bit-field is used to either enable or disable the M13 T1/E1 Framers.
If the user enables these additional T1/E1 Framers, then the XRT86SH328 will be able to perform full-blown
performance monitoring in both the Ingress and Egress Directions
.If the user disables the M13 T1/E1 Framers, then the user will only be able to perform full-block performance monitoring
on the Ingress Direction T1/E1 signals.
`
0 - Disables the M13 T1/E1 Framer blocks.
`
1 - Enables the M13 T1/E1 Framer blocks.
N
OTE
:
This bit-field is only active if the XRT86SH328 has been configured to operate in the 28-Channel Clear-Channel
T1/E1 Framer Mode.
BIT [4:1] - Unused
BIT 0 - AU-3/TUG-3 Mode Select:
This READ/WRITE bit-field is used to configure the XRT86SH328 to operate in either the AU-3 or the TUG-3 Mapping
Mode.
`
0 - Configures the XRT86SH328 to operate in the TUG-3 Mode.
`
1 - Configures the XRT86SH328 to operate in the AU-3 Mode.
N
OTE
:
This register bit is only active if the XRT86SH328 has been configured to operate in the SDH Mode.
BIT [7:4]- Unused
BIT [3:0] - Loop-back Mode[3:0]
T
ABLE
38: M
ODE
C
ONTROL
R
EGISTER
- B
YTE
0 (A
DDRESS
= 0
X
001B)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
T1/E1
De-Sync
Disable
STS-1/STS-3
& DS3
Share Serial
Interface
Additional
T1/E1
Framers
Enabled
Unused
AU-3/TUG_3*
R/W
R/W
R/W
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
T
ABLE
39: L
OOP
-
BACK
C
ONTROL
R
EGISTER
- B
YTE
0 (A
DDRESS
= 0
X
001F)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Loop-back[3:0]
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0