
XRT86SH328
PRELIMINARY
260
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
Throughout the XRT86SH328 Data Sheet, the user can control/monitor the function/performance of the T1/E1
Framer blocks consists of the following sets of Registers.
Channel Control Registers
Receive Signaling Array Registers
LAPD Buffer 0 Data Registers
LAPD Buffer 1 Data Registers
Channel - Framer Performance Monitor Registers
Channel - Framer Interrupt Register
In the XRT86SH328 Data Sheet, we indicate that the following sets of Register have the following Address
Locations.
N
OTE
:
The XRT86SH328 has a total of 28 Ingress Direction Transmit/Receive DS1/E1 Framer blocks and 28 Egress
Direction Transmit/Receive DS1/E1 Framer Blocks. Hence, the XRT86SH328 device contains a total of 56
Transmit/Receive DS1/E1 Framer blocks. Therefore, in Table _-1, the value of N can range in value from 0x01 to
0x38.
OBVIOUS QUESTION: What value of N pertains to which of the 56 T1/E1 Framer blocks within the
chip
The answer to this question depends upon whether the XRT86SH328 has been configured to operate in the
VT-Mapper (with T1/E1 Framing) or in the M13 MUX (with T1/E1 Framing) Mode.
Table 393
and
Table 394
present the values for N (for each T1/E1 Framer block) as a function of Channel Number and Signal Direction
for VT- Mapper (with T1/E1 Framing) and M13 MUX (with T1/E1 Framing) applications, respectively. Further,
Figure 18
(which depicts an illustration of the various T1/E1 Framer blocks within a given channel) can be
used as a point of reference when looking at
Table 393
and
Table 394
.
T
ABLE
392: M
EMORY
M
AP
- T1/E1 F
RAMER
B
LOCK
A
DDRESS
L
OCATION
R
EGISTER
S
ET
0xN100 - 0xN1FF
Channel X - Control Registers
0xN200 - 0xN2FF
Reserved
0xN300 - 0xN3FF
Channel X - Channel Control Registers
0xN400 - 0xN4FF
Reserved
0xN500 - 0xN5FF
Channel X - Receive Signaling Array Registers
0xN600 - 0xN6FF
Channel X - LAPD Buffer 0 Data Register
0xN700 - 0xN7FF
Channel X - LAPD Buffer 1 Data Register
0xN800 - 0xN8FF
Reserved
0xN900 - 0xN9FF
Channel X - Framer Performance Monitor Registers
0xNA00 - 0xNAFF
Reserved
0xNB00 - 0xNBFF
Channel X - Framer Interrupt Registers