
XRT86SH328
PRELIMINARY
320
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
of the following events.
Whenever it declares the DS1/E1 AIS defect condition.
Whenever it clears the DS1/E1 AIS defect condition
`
0 - Disables the "Change of DS1/E1 AIS Defect Condition" interrupt.
`
1 - Enables the "Change of DS1/E1 AIS Defect Condition" interrupt.
Bits 7 - 6 - Unused:
Bit 5 - Change of VT Path Trace Message Unstable Defect Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the "Change of VT Path Trace Message
Unstable Defect Condition" interrupt. If the user enables this interrupt, then the VT-De-Mapper block will generate this
interrupt in response to either of the following events.
Whenever the VT-De-Mapper block declares the "VT-Path Trace Message Unstable" defect condition.
Whenever the VT-De-Mapper block clears the "VT-Path Trace Message Unstable" defect condition.
`
0 - Disables the "Change of VT Path Trace Message Unstable Defect Condition" Interrupt.
`
1 - Enables the "Change of VT Path Trace Message Unstable Defect Condition" Interrupt.
Bit 4 - New VT Path Trace Message Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the "New VT Path Trace Message" Interrupt. If
the user enables this interrupt, then the VT-De-Mapper block will generate this interrupt whenever it has "accepted" a
new "VT Path Trace Message" via the incoming VT-data-stream.
`
0 - Disables the "New VT Path Trace Message" Interrupt.
`
1 - Enables the "New VT Path Trace Message" Interrupt
Bit 3 - Change of TIM-V Defect Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the "Change of TIM-V Defect
Condition" Interrupt. If the user enables this interrupt, then the VT-De-Mapper block will generate this interrupt
in response to either of the following events.
Whenever it declares the TIM-V Defect Condition
Whenever it clears the TIM-V Defect Condition
`
0 - Disables the "Change of TIM-V Defect Condition" Interrupt
`
1 - Enables the "Change of TIM-V Defect Condition" Interrupt
Bits 2 - 0 - Unused:
T
ABLE
457: C
HANNEL
C
ONTROL
- VT-D
E
-M
APPER
B
LOCK
- E
GRESS
D
IRECTION
- I
NTERRUPT
E
NABLE
R
EGISTER
(A
DDRESS
= 0
X
ND6B,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
1C)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
Change of VT
Path Trace
Message
Unstable Defect
Condition
Interrupt Enable
New VT Path
Trace Message
Interrupt Status
Change of TIM-V
Defect Condition
Interrupt Status
Unused
R/O
R/O
RUR
RUR
RUR
R/O
R/O
R/O
0
0
0
0
0
0
0
0