
XRT86SH328
PRELIMINARY
296
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT7 - G.706 Annex B CRC-4 Calculation Enable:
This bit configures the E1 receive framer block to be compliant with ITU-T G.706 Annex B for CRC-to-non-CRC
interworking detection. If Annex B is enabled, G.706 Annex B CRC-4 multi frame alignment algorithm is implemented.
If CRC-4 alignment is enabled and not achieved in 400 msec while the basic frame alignment signal is present, it is
assumed that the remote end is a non CRC-4 equipment. A CRC-to-non-CRC interworking interrupt will be generated.
`
0 = Configures the receive E1 framer block to NOT support the G.706 Annex B CRC-4 multi frame alignment
algorithm.
`
1 = Configures the receive E1 framer block to support the G.706 Annex B CRC-4 multi frame alignment algorithm.
BIT6 - Transmit CRC-4 Error:
This bit is used to force a continuous errored CRC pattern in the outbound CRC multi frame to be sent on the
transmission line. The transmit E1 framer block will implement this error by inverting the value of CRC bit (C1).
`
0 = Disabled
`
1 = Forces the transmit E1 framer block to transmit continuous errored CRC bit.
BIT [5:4] - CAS Multi Frame Select[1:0]:
These bits allow the user to select which CAS multi frame alignment declaration algorithm the receive E1 framer block
will employ, according to the table below.
10
Remote Loop-back Mode
11
Reserved
T
ABLE
434: E1 F
RAMER
B
LOCK
- F
RAMING
S
ELECT
R
EGISTER
(A
DDRESS
= 0
X
N107,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
38)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Annex B
Tx CRC-4
Error
CAS MultiFrame Sel[1:0]
CRC MultiFrame Sel[1:0]
Add Frame
ChkEnable
FAS Frame
Alignment
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
E1 Framer Block - Framing Select Register (Address = 0xN107, where N ranges in value from 0x01 to
0x38)
CAS MF A
LIGN
S
EL
[1:0]
CAS M
ULTI
F
RAME
A
LIGNMENT
D
ECLARATION
A
LGORITHM
S
ELECTED
00, 11
CAS multi frame alignment disabled.
01
The 16-Frame AlgorithmIf this alignment algorithm is selected, then the receive E1
framer block will monitor the 16th timeslot of each incoming E1 frame and will
declare CAS multi frame alignment (e.g., clear the loss of CAS multi frame defect)
condition anytime that it detects 15 consecutive E1 frames in which bits 1-4 (of time
slot 16) do not contain the CAS Multi Frame Alignment pattern, which is immedi-
ately followed by an E1 frame that DOES contain the CAS Multi Frame Alignment
pattern.
10
The 2-Frame (ITU-T G.732) AlgorithmIf this alignment algorithm is selected, then
the receive E1 framer block will declare CAS multi frame alignment anytime it
detects a single E1 frame rather than 15 consecutive E1 frames as described above
in the 16-Frame Algorithm.
Relationship between the Framer Loop-back[1:0] bit-fields and the Corresponding Loop-Back Mode
within the E1 Framer block
F
RAMER
L
OOP
-
BACK
[1:0]
R
ESULTING
L
OOP
-B
ACK
M
ODE
(
WITHIN
F
RAMER
B
LOCK
)