
XRT86SH328
PRELIMINARY
176
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
N
OTE
:
The user can determine the current state of the Transmit FIFO Underrun condition by reading the state of BIT 0
(Transmit FIFO Underrun Condition) within the DS3 Mapper Block - Status Register - Byte 0 (Address =
0x0D07).
BIT[7:4] - Reserved:
BIT 3 - Receive FIFO Overrun Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Receive FIFO Overrun Interrupt.
If this interrupt is enabled, then the DS3 Mapper block will generate an interrupt anytime it declares the Receive FIFO
Overrun condition.
`
0 - Disables this interrupt.
`
1 - Enables this interrupt.
BIT 2 - Receive FIFO Underrun Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the 'Receive FIFO Underrun interrupt.
If this interrupt is enabled, then the DS3 Mapper Block will generate an interrupt anytime it declares the Receive FIFO
Underrun condition.
`
0 - Disables this interrupt.
`
1 - Enables this interrupt.
BIT 1 - Transmit FIFO Overrun Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Transmit FIFO Overrun interrupt.
If this interrupt is enabled, then the DS3 Mapper block will generate an interrupt anytime it declares the Transmit FIFO
Overrun condition.
`
0 - Disables this interrupt.
`
1 - Enables this interrupt.
BIT 0 - Transmit FIFO Underrun Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Transmit FIFO Underrun interrupt.
If this interrupt is enabled, then the DS3 Mapper block will generate an interrupt anytime that the DS3 Mapper block
declares the Transmit FIFO Underrun condition.
`
0 - Disables this interrupt.
`
1 - Enables this interrupt.
BIT7 - Pstuff:
T
ABLE
232: DS3 M
APPER
B
LOCK
- R
ECEIVE
M
APPER
I
NTERRUPT
E
NABLE
R
EGISTER
- B
YTE
0 (A
DDRESS
=
0
X
0D0E)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Receive
FIFO Over-
run Interrupt
Enable
Receive
FIFO Under-
run Interrupt
Enable
Transmit
FIFO Over-
run Interrupt
Enable
Transmit
FIFO Under-
run Interrupt
Enable
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
T
ABLE
233: DS3 M
APPER
B
LOCK
- P
OINTER
J
USTIFICATION
S
TATUS
R
EGISTER
- B
YTE
2 (A
DDRESS
= 0
X
0D21)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PStuff
Unused
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0