
XRT86SH328
PRELIMINARY
142
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
Transport - SONET Transmit Control Register - Byte 1 (Address Location= 0x0702) is set to 1, then the STS-1/STS-3
Transmit block will load the contents of this register into the S1 byte-field, within each outbound STS-1 or STS-3 frame.
N
OTE
:
These register bits are ignored if BIT 2 (S1 Insert Method) is set to 0.
BIT [7:0] - Transmit F1 Byte Value
If the appropriate F1 Byte Insert Method is selected, then these READ/WRITE bit-fields will are used to specify the
contents of the F1 byte, within the outbound STS-1/STS-3 signal.
N
OTE
:
If BIT 3 (F1 Byte Insert Method) within the Transmit STS-1/STS-3 Transport - SONET Transmit Control Register
- Byte 1 (Address Location= 0x0702) is set to 1, then the Transmit STS-1/STS-3 TOH Processor block will load
the contents of this register into the F1 byte-field, within each outbound STS-1 or STS-3 frame. These register
bits are ignored if BIT 3 (F1 Insert Method) is set to 0.
BIT [7:0] - Transmit E1 Byte Value
If the appropriate E1 Byte Insert Method is selected, then these READ/WRITE bit-fields will are used to specify the
contents of the E1 byte, within the outbound STS-1/STS-3 signal. Note
N
OTE
:
If BIT 4 (E1 Insert Method) within the Transmit STS-1/STS-3 Transport - SONET Transmit Control Register -
Byte 1 (Address Location= 0x0702) is set to 1, then the Transmit STS-1/STS-3 TOH Processor block will load
the contents of this register into the E1 byte-field, within each outbound STS-1 or STS-3 frame. These register
bits are ignored if BIT 4 (E1 Insert Method) is set to 0.
BIT [7:0] - Transmit E2 Byte Value
If the appropriate E2 Byte Insert Method is selected, then these READ/WRITE bit-fields will are used to specify the
contents of the E2 byte, within the outbound STS-1/STS-3 signal.
N
OTE
:
If BIT 5 (E2 Insert Method) within the Transmit STS-1/STS-3 Transport - SONET Transmit Control Register -
Byte 1 (Address Location= 0x0702) is set to 1, then the Transmit STS-1/STS-3 TOH Processor block will load
the contents of this register into the E2 byte-field, within each outbound STS-1 or STS-3 frame. These register
bits are ignored if BIT 5 (E2 Insert Method) is set to 0.
T
ABLE
185: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- F1 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
073F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_F1_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
T
ABLE
186: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- E1 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
0743)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_E1_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
T
ABLE
187: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- E2 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
0747)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_E2_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0