
XRT86SH328
PRELIMINARY
194
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT7 - Detection of CP-Bit Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the Detection of CP-Bit Error Interrupt has occurred since the
last read of this register.
`
0 - Indicates that the Detection of CP-Bit Error Interrupt has NOT occurred since the last read of this register.
`
1 - Indicates that the Detection of CP-Bit Error Interrupt has occurred since the last read of this register.
N
OTE
:
This bit-field is only active if the Transmit and Receive DS3 Framer block are configured to operate in the C-Bit
Parity Framing Format.
BIT6 - Change of DS3 LOS Defect Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the Change in DS3 LOS Defect Condition Interrupt has
occurred since the last read of this register.
`
0 - Indicates that the Change in DS3 LOS Defect Condition Interrupt has NOT occurred since the last read of this
register.
`
1 - Indicates that the Change in DS3 LOS Defect Condition Interrupt has occurred since the last read of this register.
BIT 5 - Change of DS3 AIS Defect Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the Change of DS3 AIS Defect Condition Interrupt has
occurred since the last read of this register.
`
0 - Indicates that the Change of DS3 AIS Defect Condition Interrupt has NOT occurred since the last read of this
register.
`
1 - Indicates that the Change of DS3 AIS Defect Condition Interrupt has occurred since the last read of this register.
BIT 4 - Change of DS3 Idle Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the Change in DS3 Idle Condition interrupt has
occurred since the last read of this register.
`
0 - Indicates that the Change of DS3 Idle Condition Interrupt has NOT occurred since the last read of this register.
`
1 - Indicates that the Change of DS3 Idle Condition Interrupt has occurred since the last read of this register.
BIT 3 - Change of DS3 FERF/RDI Defect Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the Change of DS3 FERF/RDI Defect Condition Interrupt has
occurred since the last read of this register.
`
0 - Indicates that the Change of DS3 FERF/RDI Defect Condition interrupt has NOT occurred since the last read of
this register.
`
1 - Indicates that the Change in DS3 FERF/RDI Defect Condition interrupt has occurred since the last read of this
register.
BIT 2 - Change of AIC State Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the Change in AIC State Interrupt has occurred since the last
read of this register.
`
0 - Indicates that the Change in AIC State interrupt has NOT occurred since the last read of this register.
T
ABLE
252: DS3 F
RAMER
B
LOCK
- R
ECEIVE
DS3 I
NTERRUPT
S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
0E13)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Detection of
CP-Bit Error
Interrupt
Status
Change of
DS3 LOS
Defect
Condition
Interrupt Sta-
tus
Change of
DS3 AIS
Defect
Condition
Interrupt Sta-
tus
Change of
DS3 Idle
Condition
Interrupt
Status
Change of
DS3
FERF/RDID
efect
Condition
Interrupt
Status
Change of
AIC State
Interrupt
Status
Change of
DS3 OOF
Defect
Condition
Interrupt
Status
Detection of
P-Bit Error
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0