
PRELIMINARY
XRT86SH328
225
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
N
OTE
:
These register bits are not active if the Transmit and Receive DS3 Framer blocks have NOT been configured to
support the DS3 C-bit Parity Framing format.
BIT [7:0] - PMON DS2 # 1 - Framing Bit Error Count[7:0]/G.747 FAS Error Count[7:0]:
The function of this bit-field depends upon whether M12 MUX/De-MUX # 1 has been configured to operate in the DS2
or in the G.747 Mode.
If M12 MUX/De-MUX # 1 has been configured to operate in the DS2 Mode:
These RESET-upon-READ bit-fields reflects the cumulative number of F and M bit errors that the M12 De-MUX Block
(associated with DS2 Channel 1) has detected since the last read of this register.
If M21 MUX/De-MUX # 1 has been configured to operate in the G.747 Mode:
This RESET-upon-READ bit-fields reflects the cumulative number of FAS errors that the M12 De-MUX block
(associated with DS2 Channel 1) has detected since the last read of this register.
BIT [7:0] See
Figure 310
above, for bit descriptions
BIT [7:0] See
Figure 310
above, for bit descriptions
BIT [7:0] See
Figure 310
above for bit descriptions
T
ABLE
310: DS3 F
RAMER
B
LOCK
- PMON DS2 # 1 F
RAMING
B
IT
E
RROR
C
OUNT
R
EGISTER
(A
DDRESS
= 0
X
0E5A)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
PMON_DS2 # 1 Framing Bit Error Count[7:0]/G.747 FAS Error Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
311: DS3 F
RAMER
B
LOCK
- PMON DS2 # 2 F
RAMING
B
IT
E
RROR
C
OUNT
R
EGISTER
(A
DDRESS
= 0
X
0E5B)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
PMON_DS2 # 2 Framing Bit Error Count[7:0]/G.747 FAS Error Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
312: DS3 F
RAMER
B
LOCK
- PMON DS2 # 3 F
RAMING
B
IT
E
RROR
C
OUNT
R
EGISTER
(A
DDRESS
= 0
X
0E5C)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
PMON_DS2 # 3 Framing Bit Error Count[7:0]/G.747 FAS Error Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
313: DS3 F
RAMER
B
LOCK
- PMON DS2 # 4 F
RAMING
B
IT
E
RROR
C
OUNT
R
EGISTER
(A
DDRESS
= 0
X
0E5D)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
PMON_DS2 # 4 Framing Bit Error Count[7:0]/G.747 FAS Error Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0