
XRT86SH328
PRELIMINARY
130
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT [7:0] - Receive Positive Pointer Adjustment Count - MSB
These RESET-upon-READ bits, along with that in Receive STS-1 Path - Receive Positive Pointer Adjustment Count
Register - Byte 0 present a 16-bit representation of the number of Positive (or Incrementing) Pointer Adjustments that
the Receive STS-1 POH Processor block has detected since the last read of these registers.
N
OTE
:
This register contains the MSB (Most Significant Bits) of this 16-bit expression.
BIT [7:0] - Receive Positive Pointer Adjustment Count - LSB
These RESET-upon-READ bits, along with that in Receive STS-1 Path - Receive Positive Pointer Adjustment Count
Register - Byte 1 present a 16-bit representation of the number of Positive (or Incrementing) Pointer Adjustments that
the Receive STS-1 POH Processor block has detected since the last read of these registers.
N
OTE
:
This register contains the LSB (Least Significant Bits) of this 16-bit expression.
BIT [7:0] - J1 Byte Captured Value[7:0]
These READ-ONLY bit-fields contain the value of the J1 byte, within the most recently received STS-1/STS-3 frame.
This particular value is stored in this register for one STS-1/STS-3 frame period. During the next STS-1/STS-3 frame
period, this value will be overridden with a new J1 byte value.
BIT [7:0] - B3 Byte Captured Value[7:0]
These READ-ONLY bit-fields contain the value of the B3 byte, within the most recently received STS-1/STS-3 frame.
T
ABLE
160: R
ECEIVE
STS-1 P
ATH
- R
ECEIVE
P
OSITIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
- B
YTE
1
(A
DDRESS
= 0
X
02C6)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive Positive Pointer Adjustment Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
161: R
ECEIVE
STS-1 P
ATH
- R
ECEIVE
P
OSITIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
- B
YTE
0
(A
DDRESS
= 0
X
02C7)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive Positive Pointer Adjustment Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
162: R
ECEIVE
STS-1 P
ATH
- R
ECEIVE
J1 B
YTE
C
APTURE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
02D3)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
J1_Byte_Captured_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
T
ABLE
163: R
ECEIVE
STS-1 P
ATH
- R
ECEIVE
B3 B
YTE
C
APTURE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
02D7)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B3_Byte_Captured_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0