
XRT86SH328
PRELIMINARY
254
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
This bit serves a dual purpose. By default, this bit monitors the line code violation activity. However, if bit 7 in register
0x0101h is set High, this bit monitors the overflow status of the internal LCV counter. An interrupt will not occur unless
the LCV/OFIE is set High in register 0xN004h and the global interrupt enable has been set.
`
0 = No Alarm
`
1 = A line code violation, bipolar violation, or excessive zeros has occurred
BIT 3 - Reserved:
BIT 2 - Alarm Indication Signal:
This bit indicates the AIS activity. An interrupt will not occur unless the AISIE is set High in register 0xN004h and the
global interrupt enable has been set.
`
0 = No Alarm
`
1 = An all ones signal is detected
BIT 1 - Receive Loss of Signal:
This bit indicates the RLOS activity. An interrupt will not occur unless the RLOSIE is set High in register 0xN004h and
the global interrupt enable has been set.
`
0 = No Alarm
`
1 = An RLOS condition is present
BIT 0 - Quasi Random Pattern Detection:
This bit indicates that a QRPD has been detected. An interrupt will not occur unless the QRPDIE is set High in register
0xN004h and the global interrupt enable has been set.
`
0 = No Alarm
`
1 = A QRP is detected
N
OTE
:
These register bits are Reset Upon Read. They will be set High anytime a change in status occurs. Once these bits
are read back, they will automatically be set Low.
BIT7 - Reserved:
BIT6 - Digital Monitor Output Interrupt Enable:
`
0 = No change
`
1 = Change in status occurred
BIT 5 - FIFO Limit Status Interrupt Enable:
`
0 = No change
`
1 = Change in status occurred
BIT 4 - Line Code Violation Interrupt Enable:
`
0 = No change
`
1 = Change in status occurred
BIT 3 - Reserved:
BIT 2 - Alarm Indication Signal Interrupt Enable:
`
0 = No change
`
1 = Change in status occurred
BIT 1 - Receive Loss of Signal Interrupt Enable:
`
0 = No change
T
ABLE
380: LIU C
HANNEL
C
ONTROL
R
EGISTER
0 (A
DDRESS
= 0
X
N006)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
DMOIS
FLSIS
LCVIS
Reserved
AISDIS
RLOSIS
QRPDIS
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0