
PRELIMINARY
XRT86SH328
107
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
BIT [7:4] - Unused
BIT 3 - Check (Pointer Adjustment) Stuff Select
This READ/WRITE bit-field is used to enable/disable the SONET standard recommendation that a pointer increment or
decrement operation, detected within 3 SONET frames of a previous pointer adjustment operation (e.g., negative stuff,
positive stuff) is ignored.
`
0 - Disables this SONET standard implementation. In this mode, all pointer-adjustment operations that are detected
will be accepted.
`
1 - Enables this SONET standard implementation. In this mode, all pointer-adjustment operations that are detected
within 3 SONET frame periods of a previous pointer-adjustment operation will be ignored.
BIT 2 - Path - Remote Defect Indicator Type Select
This READ/WRITE bit-field is used to configure the Receive STS-1 POH Processor block to support either the Single-
Bit or the Enhanced RDI-P form of signaling, as described below.
`
0 - Configures the Receive STS-1 POH Processor block to support Single-Bit RDI-P.
In this mode, the Receive STS-1 POH Processor block will only monitor BIT 5, within the G1 byte (of the incoming SPE
data), in order to declare and clear the RDI-P defect condition.
`
1 - Configures the Receive STS-1 POH Processor block to support Enhanced RDI-P (ERDI-P).
In this mode, the Receive STS-1 POH Processor block will monitor bits 5, 6 and 7, within the G1 byte, in order to declare
and clear the RDI-P defect condition.
BIT 1 - REI-P Error Type
This READ/WRITE bit-field is used to specify how the Receive STS-1 POH Processor block will count (or tally) REI-P
events, for Performance Monitoring purposes. The user can configure the Receive STS-1 POH Processor block to
increment REI-P events on either a per-bit or per-frame basis.
If the user configures the Receive STS-1 POH Processor block to increment REI-P events on a per-bit basis, then it
will increment the Receive Path REI-P Error Count register by the value of the lower nibble within the G1 byte of the
incoming STS-1/STS-3 data-stream.
If the user configures the Receive STS-1 POH Processor block to increment REI-P events on a per-frame basis, then
it will increment the Receive Path REI-P Error Count register each time it receives an STS-1/STS-3 frame, in which the
lower nibble of the G1 byte (bits 1 through 4) are set to a non-zero value.
`
0 - Configures the Receive STS-1 POH Processor block to count or tally REI-P events on a per-bit basis.
`
1 - Configures the Receive STS-1 POH Processor block to count or tally REI-P events on a per-frame basis.
BIT 0 - B3 Error Type
This READ/WRITE bit-field is used to specify how the Receive STS-1 POH Processor block will count (or tally) B3 byte
errors, for Performance Monitoring purposes. The user can configure the Receive STS-1 POH Processor block to
increment B3 byte errors on either a per-bit or per-frame basis.
If the user configures the Receive STS-1 POH Processor block to increment B3 byte errors on a per-bit basis, then it
will increment the Receive Path B3 Byte Error Count register by the number of bits (within the B3 byte value) that is in
error.
If the user configures the Receive STS-1 POH Processor block to increment B3 byte errors on a per-frame basis, then
it will increment the Receive Path B3 Byte Error Count register each time it receives an STS-1/STS-3 frame that contains
an erred B3 byte.
`
0 - Configures the Receive STS-1 POH Processor block to count B3 byte errors on a per-bit basis
`
1 - Configures the Receive STS-1 POH Processor block to count B3 byte errors on a per-frame basis.
T
ABLE
131: R
ECEIVE
STS-1 P
ATH
- R
ECEIVE
C
ONTROL
R
EGISTER
- B
YTE
0 (A
DDRESS
L
OCATION
= 0
X
0283)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
CheckStuff
RDI-PType
REI-PError
Type
B3 Error
Type
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0