
XRT86SH328
PRELIMINARY
272
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT [7:0] - Receive Signaling Change - Channel n=[0:7]:
These RESET-upon-READ bit-fields indicate whether the Channel Associated Signaling data associated with Time-
Slots 0 through 7 (within the incoming DS1 data-stream) has changed since the last read of this register.
`
0 = Indicates that CAS data (for Time-Slots 0 through 7) has NOT changed since the last read of this register.
`
1 = Indicates that CAS data (for Time-Slots 0 through 7) has changed since the last read of this register.
N
OTE
:
This register is only active if the incoming DS1 data-stream is using Channel Associated Signaling.
BIT [7:0] - Receive Signaling Change - Channel n=[8:15]:
These RESET-upon-READ bit-fields indicate whether the Channel Associated Signaling data associated with Time-
Slots 8 through 15 (within the incoming DS1 data-stream) has changed since the last read of this register.
`
0 = Indicates that CAS data (for Time-Slots 8 through 15) has NOT changed since the last read of this register.
`
1 = Indicates that CAS data (for Time-Slots 8 through 15) has changed since the last read of this register.
BIT [7:0] - Receive Signaling Change - Channel n=[16:23]:
These RESET-upon-READ bit-fields indicate whether the Channel Associated Signaling data associated with Time-
Slots 16 through 23 (within the incoming DS1 data-stream) has changed since the last read of this register.
T
ABLE
403: T1 F
RAMER
B
LOCK
- R
ECEIVE
S
IGNALING
C
HANGE
R
EGISTER
- 0 (A
DDRESS
= 0
X
N10D,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
38)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
Signaling
Change -
Channel 0
Receive
Signaling
Change -
Channel 1
Receive
Signaling
Change -
Channel 2
Receive
Signaling
Change -
Channel 3
Receive
Signaling
Change -
Channel 4
Receive
Signaling
Change -
Channel 5
Receive
Signaling
Change -
Channel 6
Receive
Signaling
Change -
Channel 7
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
404: T1 F
RAMER
B
LOCK
- R
ECEIVE
S
IGNALING
C
HANGE
R
EGISTER
- 1 (A
DDRESS
= 0
X
N10E,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
38)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
Signaling
Change -
Channel 8
Receive
Signaling
Change -
Channel 9
Receive
Signaling
Change -
Channel 10
Receive
Signaling
Change -
Channel 11
Receive
Signaling
Change -
Channel 12
Receive
Signaling
Change -
Channel 13
Receive
Signaling
Change -
Channel 14
Receive
Signaling
Change -
Channel 15
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
405: T1 F
RAMER
B
LOCK
- R
ECEIVE
S
IGNALING
C
HANGE
R
EGISTER
- 2 (A
DDRESS
= 0
X
N10F,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
38)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
Signaling
Change -
Channel 16
Receive
Signaling
Change -
Channel 17
Receive
Signaling
Change -
Channel 18
Receive
Signaling
Change -
Channel 19
Receive
Signaling
Change -
Channel 20
Receive
Signaling
Change -
Channel 21
Receive
Signaling
Change -
Channel 22
Receive
Signaling
Change -
Channel 23
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0