
PRELIMINARY
XRT86SH328
99
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
BIT [7:0] - SF_BURST_TOLERANCE - LSB
These READ/WRITE bits, along with the contents of the Receive STS-1/STS-3 Transport - SF BURST Tolerance - Byte
1 registers are used to specify the maximum number of B2 byte (or BIP-24)errors that the corresponding Receive STS-
1/STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-1 or STS-3 frame
period), when determining whether or not to declare the SF (Signal Failure) defect condition.
N
OTE
:
The purpose of this feature is to are used to provide some level of B2 error burst filtering, when the Receive
STS-1/STS-3 TOH Processor block is accumulating B2 byte (or BIP-24) errors in order to declare the SF defect
condition. The user can implement this feature in order to configure the Receive STS-1/STS-3 TOH Processor
block to detect B2 bit errors in multiple Sub-Interval periods before it will declare the SF defect condition.
BIT [7:0] - SD_CLEAR_MONITOR_INTERVAL - MSB
These READ/WRITE bits, along the contents of the Receive STS-1/STS-3 Transport - SD Clear Monitor Interval - Byte
1 and Byte 0 registers are used to specify the length of the monitoring period (in terms of ms) for SD (Signal Degrade)
defect clearance.
When the Receive STS-1/STS-3 TOH Processor block is checking the incoming STS-1 or STS-3 signal in order to
determine if it should clear the SD defect condition, it will accumulate B2 byte (or BIP-24) errors throughout the user-
specified SD Defect Clearance Monitoring period. If, during this SD Defect Clearance Monitoring period, the Receive
STS-1/STS-3 TOH Processor block accumulates less B2 byte (or BIP-24) errors than that programmed into the Receive
STS-1/STS-3 Transport SD Clear Threshold register, then the Receive STS-1/STS-3 TOH Processor block will clear
the SD defect condition.
N
OTES
:
1.
The value that the user writes into these three (3) SD Clear Monitor Window Registers, specifies the
duration of the SD Defect Clearance Monitoring Period, in terms of ms.
2.
This particular register byte contains the MSB (Most significant byte) value of the three registers that
specifiy the SD Defect Clearance Monitoring period.
BIT [7:0] - SD_CLEAR_MONITOR_INTERVAL - Bits 15 through 8
T
ABLE
119: R
ECEIVE
STS-1/STS-3 T
RANSPORT
- R
ECEIVE
SF B
URST
E
RROR
T
OLERANCE
- B
YTE
0 (A
DDRESS
L
OCATION
= 0
X
0257)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_BURST_TOLERANCE[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
T
ABLE
120: R
ECEIVE
STS-1/STS-3 T
RANSPORT
- R
ECEIVE
SD C
LEAR
M
ONITOR
I
NTERVAL
- B
YTE
2 (A
DDRESS
L
OCATION
= 0
X
0259)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_MONITOR_WINDOW[23:16]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
T
ABLE
121: R
ECEIVE
STS-1/STS-3 T
RANSPORT
- R
ECEIVE
SD C
LEAR
M
ONITOR
I
NTERVAL
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
025A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_MONITOR_WINDOW[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1