
XRT86SH328
PRELIMINARY
234
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT7 - Change of M12 Loop-back Request Condition - DS1 Channel 3 Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the M12 De-MUX block (associated with DS2 Channel 0) has
generated the Change of M12 Loop-back Request Condition Interrupt, for DS1 Channel 3, since the last read of this
register. The M12 De-MUX block will generate this particular interrupt in response to either of the following events.
Whenever it detects the M12 Loop-back Request indicator for DS1 Channel 3 (within the incoming DS2
signal)
Whenever it ceases to detect the M12 Loop-back Request indicator for DS1 Channel 3 (within the incoming
DS2 signal).
`
0 - Indicates that the Change of M12 Loop-back Request Condition Interrupt, for DS1 Channel 3, has NOT occurred
since the last read of this register.
`
1 - Indicates that the Change of M12 Loop-back Request Condition Interrupt, for DS1 Channel 3, has occurred since
the last read of this register.
BIT6 - Change of M12 Loop-back Request Condition - DS1 Channel 2 Interrupt Status
See description of BIT7.
BIT 5 - Change of M12 Loop-back Request Condition - DS1 Channel 1 Interrupt Status
See description of BIT7.
BIT 4 - Change of M12 Loop-back Request Condition - DS1 Channel 0 Interrupt Status
See description of BIT7.
BIT 3 - Change of M12 Loop-back Request Condition - DS1 Channel 3 Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Change of M12 Loop-back Request
Condition Interrupt for DS1 Channel 3. If this interrupt is enabled, then the XRT86SH328 will generate an
interrupt in response to either of the following conditions.
Whenever the M12 De-MUX Block (associated with DS2 Channel 0) detects the M12 Loop-back Request
indicator for DS1 Channel 3 (within the incoming DS2 signal).
Whenever the M12 De-MUX Block ceases to detect the M12 Loop-back Request indicator for DS1 Channel 3
(within the incoming DS2 signal).
`
0 - Disables the Change of M12 Loop-back Request Condition Interrupt for DS1 Channel 3.
`
1 - Enables the Change of M12 Loop-back Request Condition Interrupt for DS1 Channel 3.
BIT 2 - Change of M12 Loop-back Request Condition - DS1 Channel 2 Interrupt Enable
See description of BIT 3.
BIT 1 - Change of M12 Loop-back Request Condition - DS1 Channel 1 Interrupt Enable
See description of BIT 3.
T
ABLE
338: DS3 F
RAMER
B
LOCK
- M12 L
OOP
-
BACK
I
NTERRUPT
S
TATUS
/E
NABLE
R
EGISTER
- 1 (A
DDRESS
=
0
X
0E93)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Change of
M12 Loop-
back
Request
Condition -
DS1
Channel 3
Interrupt
Status
Change of
M12 Loop-
back
Request
Condition -
DS1
Channel 2
Interrupt
Status
Change of
M12 Loop-
back
Request
Condition -
DS1
Channel 1
Interrupt
Status
M12 Loop-
back
Request
Condition -
DS1
Channel 0
Interrupt
Status
Change of
M12 Loop-
back
Request
Condition -
DS1
Channel 3
Interrupt
Enable
Change of
M12 Loop-
back
Request
Condition -
DS1
Channel 2
Interrupt
Enable
Change of
M12 Loop-
back
Request
Condition -
DS1
Channel 1
Interrupt
Enable
Change of
M12 Loop-
back
Request
Condition -
DS1
Channel 0
Interrupt
Enable
RUR
RUR
RUR
RUR
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0