
XRT86SH328
PRELIMINARY
230
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
These READ-ONLY bits, along with that within the DS3 Framer Block - One Second P-Bit Error Accumulation Count
Register - LSB combine to reflect the cumulative number of P-Bit errors that the Receive DS3 Framer block has detected
within the incoming DS3 data-stream, during the last one-second accumulation period. This register contains the Most
Significant byte of this 16-bit expression.
BIT [7:0] - One-Second P-Bit Error Accumulation Count[7:0]:
These READ-ONLY bits, along with that within the DS3 Framer Block - One Second P-Bit Error Accumulation Count
Register - MSB combine to reflect the cumulative number of P-Bit errors that the Receive DS3 Framer block has
detected within the incoming DS3 data-stream, during the last one-second accumulation period. This register contains
the Least Significant byte of this 16-bit expression.
BIT [7:0] - One-Second CP-Bit Error Accumulation Count[15:8]:
These READ-ONLY bits, along with that within the DS3 Framer Block - One Second CP-Bit Error Accumulation Count
Register - LSB combine to reflect the cumulative number of CP-Bit errors that the Receive DS3 Framer block has
detected within the incoming DS3 data-stream, during the last one-second accumulation period. This register contains
the Most Significant byte of this 16-bit expression.
N
OTE
:
This register is only active if the Transmit and Receive DS3 Framer blocks have been configured to operate in
the DS3, C-bit Parity Framing format.
BIT [7:0] - One-Second CP-Bit Error Accumulation Count[7:0]:
These READ-ONLY bits, along with that within the DS3 Framer Block - One Second CP-Bit Error Accumulation Count
Register - MSB combine to reflect the cumulative number of CP-Bit errors that the Receive DS3 Framer block has
detected within the incoming DS3 data-stream, during the last one-second accumulation period. This register contains
the Least Significant byte of this 16-bit expression.
N
OTE
:
This register is only active if the Transmit and Receive DS3 Framer blocks have been configured to operate in
the DS3, C-bit Parity Framing format.
T
ABLE
330: DS3 F
RAMER
B
LOCK
- P-B
IT
E
RROR
O
NE
S
ECOND
A
CCUMULATOR
R
EGISTER
- LSB (A
DDRESS
=
0
X
0E71)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
One_Second_P_Bit_Error_Accum_Count[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
T
ABLE
331: DS3 F
RAMER
B
LOCK
- CP-B
IT
E
RROR
O
NE
S
ECOND
A
CCUMULATOR
R
EGISTER
- MSB (A
DDRESS
=
0
X
0E72)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
One_Second_CP_Bit_Error_Accum_Count[15:8]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
T
ABLE
332: DS3 F
RAMER
B
LOCK
- CP-B
IT
E
RROR
O
NE
S
ECOND
A
CCUMULATOR
R
EGISTER
- LSB (A
DDRESS
=
0
X
0E73)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
One_Second_CP_Bit_Error_Accum_Count[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0