
XRT86SH328
PRELIMINARY
312
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT[7:0] - REI-V Event Count[7:0]:
These RESET-upon-READ bit-fields, along with those within the VT Mapper Block - Egress Direction - REI-V Event
Count Register - Byte 1, presents a 12-bit expression that reflects the number of REI-V Events that the Receive VT-De-
Mapper Block has detected (within the incoming VT-data-stream) since the last read of this register.
These particular bit-fields are the eight least significant bit-fields within this 12-bit expression.
N
OTE
:
The user must induce a "0 to 1 transition" within Bit 3 (Latch Count) within the "Global VT-Mapper Block - VT
Mapper Block Control Register (Address = 0x0C03) prior to reading out the contents within these bit-fields.
BIT 7 - 4 - Unused:
This READ/WTC bit-field indicates whether or not the Change of Receive APS Value event has occurred (within this
Tributary) since the last time that the user has written a 1 to clear this bit-field. The Receive VT-De-Mapper block will
declare the Change of Receive APS Value whenever it has accepted a new value from the K4 bytes within the incoming
VT data-stream.
`
0 - Indicates that the Change of Receive APS Value event has NOT occurred since the last time the user has written
a 1 to clear this bit-field.
`
1 - Indicates that the Change of Receive APS Value event has occurred since the last time the user has written a 1
to clear this bit-field.
BIT 3 - 0 - Receive APS Value[3:0]:
These four (4) READ-ONLY bit-field reflects the APS value that the VT-De-Mapper block has received (via Bits 1
through 4, within the K4 byte) and has validated.
BIT 7 - Change of DS1/E1 AIS Defect Condition - Event Mask:
This READ/WRITE bit-field permits the user to either enable or disable the "Change of DS1/E1 AIS Defect Condition"
event to/from causing the "Change of DS1/E1 AIS Defect Condition" interrupt to be generated. If the user enables this
T
ABLE
447: C
HANNEL
C
ONTROL
- VT-D
E
-M
APPER
B
LOCK
- E
GRESS
D
IRECTION
- REI-V E
VENT
C
OUNT
R
EGISTER
-
B
YTE
0 (A
DDRESS
= 0
X
ND4F,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
1C)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI-V Event Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
448: C
HANNEL
C
ONTROL
- VT-M
APPER
B
LOCK
- E
GRESS
D
IRECTION
- R
ECEIVE
APS R
EGISTER
- B
YTE
0
(A
DDRESS
= 0
X
ND53,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
1C)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
Receive APS Value[3:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
T
ABLE
449: C
HANNEL
C
ONTROL
- VT-M
APPER
B
LOCK
- I
NGRESS
D
IRECTION
- T
RANSMIT
APS R
EGISTER
- B
YTE
2
(A
DDRESS
= 0
X
ND56,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
1C)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
DS1/E1 AIS
- Event Mask
DS1/E1 LOC
-Event Mask
Reserved
Transmit
Elastic Store
Overflow
Reserved
R/W
R/O
R/O
R/O
RUR
R/O
R/O
R/O
0
0
0
0
0
0
0
0