
XRT86SH328
PRELIMINARY
116
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT 2 - Unused
BIT 1 - Change in TIM-P (Trace Identification Mismatch) Defect Condition Interrupt
This READ/WRITE bit-field is used to either enable or disable the Change in TIM-P Condition interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either
of the following events.
If the TIM-P defect condition is declared.
If the TIM-P defect condition is cleared.
`
0 - Disables the Change in TIM-P Defect Condition Interrupt.
`
1 - Enables the Change in TIM-P Defect Condition Interrupt.
BIT 0 - Change in Path Trace Message Unstable Defect Condition Interrupt Status
This READ/WRITE bit-field is used to either enable or disable the Change in Path Trace Message Unstable Defect
Condition Interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either
of the following events.
Whenever the Receive STS-1 POH Processor block declares the Path Trace Message Unstable Defect
Condition.· Whenever the Receive STS-1 POH Processor block clears the Path Trace Message Unstable
Defect Condition.
`
0 - Disables the Change in Path Trace Message Unstable Defect Condition interrupt.
`
1 - Enables the Change in Path Trace Message Unstable Defect Condition interrupt.
BIT 7 - New Path Trace Message Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the New Path Trace Message Interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it has
accepted (or validated) and new Path Trace Message.
`
0 - Disables the New Path Trace Message Interrupt.
`
1 - Enables the New Path Trace Message Interrupt.
BIT 6 - Detection of REI-P Event Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Detection of REI-P Event Interrupt.
If this interrupt is enabled, then he Receive STS-1 POH Processor block will generate an interrupt anytime it detects
an REI-P condition in the coming STS-1/STS-3 data-stream.
`
0 - Disables the Detection of REI-P Event Interrupt.
`
1 - Enables the Detection of REI-P Event Interrupt.
BIT 5 - Change in UNEQ-P (Path - Unequipped) Defect Condition Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Change in UNEQ-P Defect Condition interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either
of the following conditions
T
ABLE
138: R
ECEIVE
STS-1 P
ATH
- SONET R
ECEIVE
P
ATH
I
NTERRUPT
E
NABLE
- B
YTE
1 (A
DDRESS
L
OCATION
=
0
X
028E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
New Path
Trace Mes-
sage Inter-
rupt Enable
Detection of
REI-P Event
Interrupt
Enable
Change in
UNEQ-P
Defect Con-
dition Inter-
rupt Enable
Change in
PLM-P
Defect Con-
dition Inter-
rupt Enable
New C2 Byte
Interrupt
Enable
Change in
C2 Byte
Unstable
Defect Con-
dition Inter-
rupt Enable
Change in
RDI-P
Unstable
Defect Con-
dition Inter-
rupt Enable
New RDI-
PValue Inter-
rupt Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0