
XRT86SH328
PRELIMINARY
192
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT 4 - DS3 FERF/RDI Defect Declared:
This READ-ONLY bit-field indicates whether or not the Receive DS3 Framer block is currently declaring the FERF/RDI
defect condition.
`
0 - Indicates that the Receive DS3 Framer block is NOT currently declaring the FERF/RDI defect condition.
`
1 - Indicates that the Receive DS3 Framer block is currently declaring the FERF/RDI defect condition.
BIT 3 - Received AIC State:
This READ-ONLY bit-field reflects the current state of the AIC bit-field within the incoming DS3 data-stream.
`
0 - Indicates that the Receive DS3 Framer block has received at least 2 consecutive M-frames that have the AIC bit-
field set to 0.
`
1 - Indicates that the Receive DS3 Framer block has received at least 63 consecutive M-frames that have the AIC bit-
field set to 1.
BIT[2:0] - Received FEBE[2:0] Value:
These READ-ONLY bit-fields reflects the FEBE value within the most recently received DS3 frame.
`
Received FEBE[2:0] = [1, 1, 1] reflects a normal condition. All other values for Received FEBE[2:0] indicates an erred
condition at the remote terminal equipment.
N
OTE
:
This bit-field is only active if the Transmit/Receive DS3 Framer blocks have been configured to operate in the
C-bit Parity Framing format.
BIT7 - Detection of CP-Bit Error Interrupt Enable:
This READ/WRITE bit-field is used to either enable or disable the Detection of CP-bit Error interrupt, within the
XRT86SH328. If this interrupt is enabled, then the Receive DS3 Framer block will generate an interrupt anytime it
detects at least one CP-bit error within the incoming DS3 data-stream.
`
0 - Disables the Detection of CP-Bit Error Interrupt.
`
1 - Enables the Detection of CP-Bit Error Interrupt.
N
OTE
:
This bit-field is only active if the Transmit and Receive DS3 Framer blocks have been configured to operate in
the C-bit Parity framing format.
BIT6 - Change of DS3 LOS Defect Condition Interrupt Enable:
This READ/WRITE bit-field is used to either enable or disable the Change in DS3 LOS (Loss of Signal) defect condition,
within the XRT86SH328. If this interrupt is enabled, then the Receive DS3 Framer block will generate an interrupt in
response to either of the following conditions.
The instant that the Receive DS3 Framer block declares the LOS defect condition.
The instant that the Receive DS3 Framer block clears the LOS defect condition.
`
0 - Disables the Change in DS3 LOS Defect Condition Interrupt.
`
1 - Enables the Change in DS3 LOS Defect Condition Interrupt.
BIT 5 - Change of DS3 AIS Defect Condition Interrupt Enable:
This READ/WRITE bit-field is used to either enable or disable the Change in DS3 AIS (Alarm Indication Signal) defect
condition interrupt within the XRT86SH328. If this interrupt is enabled, then the Receive DS3 Framer block will generate
T
ABLE
251: DS3 F
RAMER
B
LOCK
- R
ECEIVE
DS3 I
NTERRUPT
E
NABLE
R
EGISTER
(A
DDRESS
= 0
X
0E12)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Detection of
CP-Bit Error
Interrupt
Enable
Change of
DS3 LOS
Defect
Condition
Interrupt
Enable
Change of
DS3 AIS
Defect
Condition
Interrupt
Enable
Change of
DS3 Idle
Condition
Interrupt
Enable
Change of
DS3
FERF/RDID
efect
Condition
Interrupt
Enable
Change of
AIC State
Interrupt
Enable
Change of
DS3 OOF
Defect
Condition
Interrupt
Enable
Detection of
P-Bit Error
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0