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參數(shù)資料
| 型號： | CD1284 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| 中文描述： | 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口 |
| 文件頁數(shù)： | 81/176頁 |
| 文件大小： | 2255K |
| 代理商： | CD1284 |
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IEEE 1284-Compatible Parallel Interface Controller
—
CD1284
Datasheet
81
Negotiation Status Register
After any IEEE-1284 negotiation or termination, the current protocol status can be read in the
NSR. NegOK and NegFl (bits 7:6) indicate successful and failed attempts. Invalid (bit 4) indicates
that the mode terminated from an invalid state. Termination from valid states are reported as
successful with NegOK.
A 4-bit code is displayed in the lower portion of the NSR to indicate the results of successful
negotiation. This 4-bit code also indicates the mode that the interface was in when an invalid
termination was detected, as well as a failed negotiation. Interrupts indicating a successful
negotiation into a reverse mode should prompt the CPU to load reverse data into the FIFO.
Special Command Register
The bits in the SCR cause actions on the parallel port. SetPs and ClrPs (bits 3:2) control data
movement into the CD1284 from the remote master. In Compatibility mode this function posts
error status to the remote. Errors can only be presented to the master by the slave during the active
BUSY period. SetPs causes the CD1284 to stop transfers by asynchronously asserting the BUSY
signal. To protect against the possibility of data loss, one more byte can be strobed into the CD1284
after BUSY goes active due to the setting of SetPs. When the error status is delivered, ClrPs
restores the parallel interface to the normal running state.
EPIrq sends an interrupt pulse in EPP mode. Setting the RevRq bit indicates to the host parallel
port that data is available for reverse transfer in either Compatible or ECP mode. These operations
are further described in the relevant protocol sections.
5.12.10
Data Transfers
In Compatibility mode, incoming HstClk (STROBE*) pulses activate PerBsy (BUSY), and the
data on the PD lines is held in latches. PerBsy protects the data latches by signaling the master it is
not ready for more transfers. After the HstClk pulse ends, a pulse is sent on PerClk (ACK*) to
acknowledge the receipt of the data into the holding latches. After the data moves from the latches
to the FIFO, PerBsy goes low to signal readiness for the next character.
All other data transfer modes require IEEE-1284 negotiations.
5.12.11
Compatible Mode Status
The IEEE 1284 specification requires that the three Compatibility mode status lines (SELECT,
FAULT*, and PError) must not be asserted unless PerBsy (BUSY) is high. PerBsy can only be
activated in response to a received character, and must remain high until the status condition (for
example, paper out) changes.
To send these status signals to the master device, set the SetPs bit (SCR[2]) and the appropriate bit
in the OVR for each of the status signals. The SetPs bit activates PerBsy, which remains active
until ClrPs (SCR[3]) is set. No data is lost in this operation.
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