參數(shù)資料
型號： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口
文件頁數(shù)： 20/176頁
文件大小： 2255K
代理商： CD1284
CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
20
Datasheet
RXD3
I
1
17
TXD2
O
1
18
High
RXD2
I
1
19
RTS2*
O
1
26
High
RTS3*
O
1
21
High
DTR2*
O
1
25
High
DTR3*
O
1
20
High
CTS2*
I
1
27
CTS3*
I
1
22
DSR2*
I
1
28
DSR3*
I
1
23
CD2*
I
1
29
CD3*
I
1
24
RI2*
I
1
15
RI3*
I
1
14
N/C
–
1
74
Table 1. Pin Descriptions
(Sheet 1 of 4)
Symbol
Pin No.
Type
Description
RESET*
79
I
ACTIVE-LOW RESET:
This input initializes the device to the default condition. All
internal registers are set to their reset condition and all transfer operations are set to
the default state.
OUTEN
83
I
OUTPUT ENABLE:
This pin must be
‘
1
’
to enable output pin functions. When OUTEN
is
‘
0
’
, it forces all output pins to remain in a tristate condition. Typically, OUTEN is used
only for test purposes. User designs must tie this pin to V
CC
through a pull-up resistor.
CLK
73
I
SYSTEM CLOCK:
This input has a 25-MHz maximum; 16 MHz is the recommended
minimum for satisfactory device performance.
CLK/2
80
O
SYSTEM CLOCK DIVIDED BY TWO OUTPUT:
This signal is equivalent to the
internal operating clock of the device.
DB[15:0]
92
–
99, 2
–
9
I/O
BIDIRECTIONAL DATA BUS:
Only DMA transfers and writes to the DMA Buffer
register are true 16-bit operations. During all register writes other than to the DMA
Buffer register, bits [7:0] are written to the addressed register. Register reads duplicate
the register contents on both the lower byte [7:0] and upper byte [15:8].
A[6:0]
84
–
90
I
ADDRESS BUS:
Together with CS* or one of the SVCACK* inputs and DS*, this input
selects an On-Chip register for a read or write operation or an acknowledgment to an
service request.
R/W*
76
I
READ/WRITE*:
This input must be
‘
1
’
for a register read operation, and must be
‘
0
’
for
a register write. R/W* is ignored for DMA operations.
CS*
78
I
ACTIVE-LOW CHIP SELECT:
When active, the input CS* combines with DS*,
initiates an I/O cycle with the CD1284. CS* must be
‘
1
’
during DMA read/write
operations.
Pin Name
Type
Number
of Pins
Pin
Number
Reset
State
(Sheet 3 of 3)
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