參數(shù)資料
型號： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口
文件頁數(shù)： 128/176頁
文件大?。?/td> 2255K
代理商： CD1284
CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
128
Datasheet
7.4.5
Channel Option Register 5
7.4.6
Local Interrupt Vector Register
The LIVR is used only during hardware-activated service-acknowledge cycles. Host software
loads desired information into the most-significant five bits; the least-significant three bits are not
used. When the CD1284 is setting up a service request, it overlays the five most-significant bits of
the LIVR into appropriate interrupt vector register (RIVR, TIVR, PIVR, and MIVR) and sets the
least-significant three bits as required for the service request vector type. (See RIVR, TIVR, PIVR,
and MIVR descriptions). Refer to
Section 7.7.5 on page 138
for a more detailed description of this
register.
Register Name: COR5
Register Description: Channel Option Register 5
Access: Read/Write
Bit 7
Bit 6
ISTRIP
LNE
8-Bit Hex Address: 1F
Default Value: 00
Bit 5
CMOE
Bit 4
0
Bit 3
0
Bit 2
EBD
Bit 1
ONLCR
Bit 0
OCRNL
Bit
Description
7
ISTRIP:
This bit enables stripping of the most-significant bit (bit 7) on all received characters.
‘
1
’
enables the
function.
6
LNext Enable:
When this bit is set, characters following an LNext character (as programmed by the LNC
register) are not processed as a special character.
5
Character Matching on Error:
If this bit is set, character matching occurs on both good and error characters.
If the bit is cleared, matching occurs on good characters only.
4:3
These bits must always be
‘
0
’
.
2
End of Break Detect:
If this bit is set, the CD1284 after detecting and reporting a line-break condition,
searches for the end of a break and reports it by an exception service request with the End of Break status in
the RDSR (see RDSR description
Section 7.2.4 on page 115
).
1:0
Carriage Return (CR) and New Line (NL) Processing
–
Transmit: These two bits define any actions taken on
characters in the transmit data stream.
Register Name: LIVR
Register Description: Local Interrupt Vector
Access: Read/Write
Bit 7
Bit 6
X
X
8-Bit Hex Address: 18
Default Value: 00
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
IT2
Bit 1
IT1
Bit 0
IT0
ONLCR
OCRNL
Action
0
0
No action.
0
1
Transmit CR changed to NL.
1
0
Transmit NL changed to CRNL.
1
1
Transmit CR changed to NL; NL changed to CRNL.
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