參數(shù)資料
型號： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口
文件頁數(shù)： 113/176頁
文件大?。?/td> 2255K
代理商： CD1284
IEEE 1284-Compatible Parallel Interface Controller
—
CD1284
Datasheet
113
7.1.12
Transmit Interrupting Channel Register
See
Section 7.1.5 on page 109
, the description of the MICR, for details on the TICR.
7.1.13
Transmit Interrupt Register
See
Section 7.1.6 on page 110
, the description of the MIR, for details on the TIR.
7.2
Virtual Registers
The CD1284 has two operational contexts:
Normal:
Allows host access to most registers and any channel
Service-acknowledge:
Allows host access to some registers specific to the channel requesting
service.
This special set of registers is called Virtual because they are only available to host access and valid
during this service-acknowledge context. At all other times, their contents are undefined and must
not be written to by host software.
The use of Virtual registers and context switching allows the CD1284 to maintain all channel-
specific information. To access the registers pertinent to the channel being serviced, it is not
necessary for the host to make any changes to the device registers.
The service-acknowledge context can be entered in two ways: 1) by activating one of the
SVCACK* input pins (hardware-activated); 2) by the host software when the contents of any one
of TIR, RIR, MIR, or PIR are copied into the CAR during a Poll-mode acknowledge cycle.
Chapter
5.0
discusses the differences between these two modes.
2
Service Request Modem:
‘
1
’
indicates request pending.
1
Service Request Transmit:
‘
1
’
indicates request pending.
0
Service Request Receive:
‘
1
’
indicates request pending.
Register Name: TICR
Register Description: Transmit Interrupting Channel
Access: Read/Write
8-Bit Hex Address: 45
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
C1
C0
X
X
Bit
Description
Register Name: TIR
Register Description: Transmit Interrupt
Access: Read/Write
Bit 7
Bit 6
TxIreq
Txbusy
8-Bit Hex Address: 6A
Default Value: 10
Bit 5
Txunfair
Bit 4
1
Bit 3
0
Bit 2
0
Bit 1
ch[1]
Bit 0
ch[0]
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