參數(shù)資料
型號： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口
文件頁數(shù)： 138/176頁
文件大?。?/td> 2255K
代理商： CD1284
CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
138
Datasheet
These resisters can be read through DMA acknowledge or PIO cycles, however, the DMABUF
registers can only be read when the DMAREQ* signal is active. If DMAREQ* is inactive, the
DMABUF registers will be empty. DMAfull (HRSR[3]) indicates if the DMABUF register is
empty when DMAREQ* is active.
7.7.4
Firmware Revision Code Holding Register Status Register
The HRSR is a read-only register that indicates current data pipeline status. This register is not
directly set to any particular value by a device reset, but reflects the current state of bits in other
registers.
7.7.5
Local Interrupt Vector Register
This read/write register can be initialized to any desired value and, when read in the normal context
(that is, not a service acknowledge context), the same value will be returned. The upper 5 bits are
copied into the appropriate vector register (MIVR, PIVR, TIVR, or RIVR) when the corresponding
SVCACK* signal is activated
and
an SVCREQ* of the same type is active. During this hardware-
activated service acknowledge read cycle, the appropriate vector register (MIVR, PIVR, TIVR, or
RIVR) is driven onto the data bus, DB[7:0].
Register Name: HRSR
Register Description: Holding Register Status
Access: Read only
8-Bit Hex Address: 34
Default Value: 04
Bit 7
HR1full
Bit 6
HR1tag
Bit 5
HR2full
Bit 4
HR2tag
Bit 3
DMAfull
Bit 2
Bit 1
DMAact
Bit 0
Ctnot0
DMAmpty
Bit
Description
7:6
Holding Register 1 Full and Holding Register 1 Tagged:
These two bits indicate status of PFHR1. Bit 7
indicates that the register contains data; bit 6 indicates that the data is tagged. Bits 7 and 6 can be set
simultaneously.
5:4
Holding Register 2 Full and Holding Register 2 Tagged:
These two bits indicate status of PFHR2. Bit 5
indicates that the register contains data; bit 4 indicates that the data is tagged. Bits 5 and 4 can be set
simultaneously.
3:2
DMA Buffer Full and DMA Buffer Empty:
These two bits indicate status of the DMA transfer buffer (DMA
buffer). Bit 3 indicates that the register contains data; bit 2 indicates that it is empty.
1
DMA Active:
When this bit is set, it indicates that the DMA handshake is active and a DMA service has been
requested but is not yet complete (DMAREQ* active
–
waiting for DMAACK*).
0
Count Not Zero:
This bit indicates that the RLE counter is not zero, thus run-length encoding/decoding is in
progress.
Register Name: LIVR
Register Description: Local Interrupt Vector
Access: Read/Write
Bit 7
Bit 6
8-Bit Hex Address: 18
Default Value: 00
Bit 5
Bit 4
Bit 3
Bit 2
IT2
Bit 1
IT1
Bit 0
IT0
User-Defined Bits
相關PDF資料
PDF描述
CD13002 NPN SILICON PLANAR EPITAXIAL, HIGH VOLTAGE FAST SWITCHING POWER TRANSISTOR
CD14538 CMOS DUAL PRECISION MONOSTABLE MULTIVIBRATOR
CD14538BMS CMOS Dual Precision Monostable Multivibrator
CD15B-15MB CD105B
CD105B CD105B
相關代理商/技術參數(shù)
參數(shù)描述
CD-12AFFM-QL8D01 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10
CD-12AFFM-QR8D01 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10
CD-12AMMM-QL8D01 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10
CD-12BFFA-LL7001 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10
CD-12BFFA-QL8SP0 功能描述:CONN PLUG FMALE 12POS CRIMP 制造商:amphenol ltw 系列:X-Lok 包裝:散裝 零件狀態(tài):在售 連接器類型:插頭，母型插口 針腳數(shù):12（數(shù)據(jù)） 外殼尺寸 - 插件:C 外殼尺寸，MIL:- 安裝類型:自由懸掛 端接:壓接 緊固類型:推挽式 朝向:帶標記 侵入防護:IP68 - 防塵，防水 外殼材料，鍍層:聚酰胺（PA），尼龍，玻璃纖維增強型 觸頭鍍層:金 特性:后殼，應力消除 電壓 - 額定:- 額定電流:5A 觸頭鍍層厚度:- 工作溫度:-20°C ~ 80°C 標準包裝:1
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*